CONVERSION OF THIN TRANSISTOR ELEMENTS FROM SILICON TO SILICON GERMANIUM

• US 20140175543A1
• Filed: 12/20/2012
• Published: 06/26/2014
• Est. Priority Date: 12/20/2012
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Glass, Glenn A., Aubertine, Daniel B., Murthy, Anand S., Thareja, Gaurav, Cea, Stephen M.
• Granted Patent: US 8,957,476 B2
• Time in Patent Office: Days
• US Class Current: 257/337
• CPC Class Codes: H01L 21/823431 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 27/0886 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/0669 Nanowires or nanotubes carbon nanotubes as material of solid-state device active part H10K85/211
• CPC Class Codes: H01L 29/1033 with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with channel and gate aligned in the lengthwise direction H01L29/42376; with buried channel H01L29/7838
• CPC Class Codes: H01L 29/16 including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/7853 the body having a non-rectangular crossection

Abstract

Embodiments of the present disclosure provide techniques and configurations associated with conversion of thin transistor elements from silicon (Si) to silicon germanium (SiGe). In one embodiment, a method includes providing a semiconductor substrate having a channel body of a transistor device disposed on the semiconductor substrate, the channel body comprising silicon, forming a cladding layer comprising germanium on the channel body, and annealing the channel body to cause the germanium to diffuse into the channel body. Other embodiments may be described and/or claimed.

Claims

1. A method comprising:

providing a semiconductor substrate having a channel body of a transistor device disposed on the semiconductor substrate, the channel body comprising silicon;

forming a cladding layer comprising germanium on the channel body;

forming a capping layer on the cladding layer to cover substantially all material of the cladding layer to prevent flow of the germanium during annealing of the channel body; and

annealing the channel body to cause the germanium to diffuse into the channel body, wherein forming the capping layer is performed prior to annealing the channel body and wherein annealing the channel body is performed with the capping layer disposed on the cladding layer.

2. The method of claim 1, wherein the germanium comprises from 70% to 100% of material of the cladding layer prior to annealing.

3. The method of claim 1, wherein forming the capping layer comprises depositing a nitride or oxide material on the cladding layer.

4. The method of claim 1, further comprising:

removing the capping layer; and

forming a gate of the transistor on the channel body.

5. The method of claim 1, wherein:

the channel body of the transistor is a first channel body of a fin structure;

the semiconductor substrate has a second channel body of another fin structure disposed on the semiconductor substrate and electrically insulative material disposed on the semiconductor substrate between the first channel body and the second channel body; and

forming the cladding layer comprises selectively depositing material of the cladding layer to form a cladding layer on the first channel body and the second channel body, but not the electrically insulative material.

6. The method of claim 5, wherein:

the first channel body and the second channel body are channel bodies of a plurality of p-channel bodies;

the semiconductor substrate has a plurality of n-channel bodies disposed on the semiconductor substrate; and

forming the cladding layer comprises depositing the material of the cladding layer on the plurality of p-channel bodies without depositing the material of the cladding layer on the plurality of n-channel bodies.

7. The method of claim 1, wherein forming the cladding layer comprises depositing germanium to form a conformal cladding layer composed of germanium in an amorphous configuration on the channel body.

8. The method of claim 7, wherein:

the channel body is composed of single crystal silicon; and

annealing the channel body is performed in an inert ambient and forms silicon germanium (SiGe) alloy from the deposited germanium and the silicon of the channel body.

9. The method of claim 1, wherein forming the cladding layer comprises depositing germanium to form a faceted cladding layer composed of germanium in a single crystal or polycrystalline configuration on the channel body.

10. The method of claim 1, wherein:

forming the cladding layer comprises depositing silicon germanium (Si_1-xGe_x) to form a cladding layer composed of silicon germanium on the channel body; and

x is a value between 0.15 and 0.7 representing a ratio of germanium to silicon.

11. The method of claim 10, wherein depositing the silicon germanium comprises depositing silicon germanium to form a conformal or faceted layer composed of silicon germanium in a single crystal, polycrystalline, or amorphous configuration on the channel body.

12. The method of claim 10, wherein annealing the channel body is performed in an oxidizing ambient and forms a layer of oxide on the silicon germanium, the method further comprising:

removing the layer of oxide from the silicon germanium; and

forming a gate of the transistor on the channel body.

13. The method of claim 1, further comprising:

doping material of the cladding layer with an n-type dopant.

14. The method of claim 1, wherein annealing the channel body provides a channel body composed primarily or entirely of silicon germanium (SiGe) alloy.

15. The method of claim 1, wherein annealing the channel body is performed at a temperature greater than 700°

C.

31. The method of claim 1, further comprising:

forming the channel body by patterning a hardmask, wherein the capping layer and the hardmask are separately formed.

16-30. -30. (canceled)