SHAPE ENHANCED PIN READ HEAD MAGNETIC TRANSDUCER WITH STRIPE HEIGHT DEFINED FIRST AND METHOD OF MAKING SAME

• US 20140175576A1
• Filed: 12/21/2012
• Published: 06/26/2014
• Est. Priority Date: 12/21/2012
• Status: Active Grant

• Current Assignee: JP Morgan Chase Bank, N.A. (JP Morgan Chase & Co)
• Original Assignee: HGST Netherlands B.V. (Western Digital Corporation)
• Inventors: AHN, Yongchul, DANG, Xiaozhong, HSU, Yimin, LE, Quang, LEONG, Thomas, LIAO, Simon, LIU, Guangli, PENTEK, Aron
• Granted Patent: US 8,836,059 B2
• Time in Patent Office: Days
• US Class Current: 257/421
• CPC Class Codes: B82Y 10/00 Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
• CPC Class Codes: G11B 2005/3996 large or giant magnetoresistive effects [GMR], e.g. as generated in spin-valve [SV] devices
• CPC Class Codes: G11B 5/3909 Arrangements using a magnetic tunnel junction
• CPC Class Codes: G11B 5/3932 Magnetic biasing films
• CPC Class Codes: H01L 21/02104 Forming layers deposition in general C23C; crystal growth in general C30B
• CPC Class Codes: H01L 29/82 controllable by variation of the magnetic field applied to the device

Abstract

The present invention generally relates to a magnetic sensor in a read head having a hard or soft bias layer that is uniform in thickness within the sensor stack. The method of making such sensor is also disclosed. The free layer stripe height is first defined, followed by defining the track width, and lastly the pinned layer stripe height is defined. The pinned layer and the hard or soft bias layer are defined in the same process step. This approach eliminates a partial hard or soft bias layer and reduces potential instability issues.

Claims

1. A magnetic head, comprising:

a sensor stack formed over a substrate, the sensor stack having a pinned layer, a free layer and a non-magnetic layer sandwiched between the pinned layer and the free layer;

a first hard or soft bias layer disposed within a first channel, positioned within the sensor stack and having a substantially uniform thickness, wherein the first channel is bound by the free layer, the non-magnetic layer, the pinned layer and the substrate; and

a second hard or soft bias layer disposed within a second channel, positioned within the sensor stack and having a substantially uniform thickness, wherein the second channel is bound by the free layer, the non-magnetic layer, the pinned layer and the substrate.

2. The magnetic head of claim 1, wherein the non-magnetic layer comprises MgO for tunnel junction magnetoresistive (TMR) barrier or AgSn for current perpendicular to the plane (CPP) spacer.

3. The magnetic head of claim 2, further comprising a first barrier layer disposed within the first channel on the substrate, wherein the first hard or soft bias layer is disposed on the first barrier layer.

4. The magnetic head of claim 3, wherein the first barrier layer comprises SiN, TaOx, AlOx, or SiOxNy, the first hard bias layer comprises CoFe, CoPt, FePt, or CoPtCr, and the first soft bias layer comprises NiFe, CoFe, NiFeMo, alloys of these compounds, or any combination thereof.

5. The magnetic head of claim 4, further comprising a second barrier layer disposed within the second channel on the substrate, wherein the second hard or soft bias layer is disposed on the second barrier layer.

6. The magnetic head of claim 5, wherein the second barrier layer comprises SiN, TaOx, AlOx, or SiOxNy, the second hard bias layer comprises CoFe, CoPt, FePt, or CoPtCr, and the second soft bias layer comprises NiFe, CoFe, NiFeMo, alloys of these compounds, or any combination thereof.

7. A method of forming a magnetic head, comprising:

forming a sensor stack over a substrate, wherein the sensor stack has at least a pinned layer, a non-magnetic layer disposed on the pinned layer, and a free layer disposed on the non-magnetic layer;

removing a first portion of the sensor stack to expose the pinned layer;

depositing a first dielectric layer, wherein the first dielectric layer comprises one or more dielectric materials;

removing a second portion of the sensor stack to expose the substrate and form one or more channels;

depositing a barrier layer in the one or more channels;

depositing a hard or soft bias layer over the barrier layer within the one or more channels;

removing a third portion of the sensor stack to expose the substrate; and

depositing a second dielectric layer, wherein the second dielectric layer comprises one or more dielectric materials and the hard or soft bias layer has a substantially uniform thickness within the one or more channels.

8. The method of claim 7, wherein the first portion of the sensor stack comprises the non-magnetic layer and the free layer.

9. The method of claim 8, wherein the second portion of the sensor stack comprises the pinned layer, the non-magnetic layer, the free layer and the first dielectric layer.

10. The method of claim 9, wherein the third portion of the sensor stack comprises the pinned layer, the first dielectric layer and the hard or soft bias layer.

11. The method of claim 7, wherein the barrier layer comprises SiN, TaOx, AlOx, or SiOxNy, the hard bias layer comprises CoFe, CoPt, FePt, or CoPtCr, and the soft bias layer comprises NiFe, CoFe, NiFeMo, alloys of these compounds, or any combination thereof.

12. The method of claim 7, wherein the first dielectric layer is selected from the group consisting of AlO_x, TaO_x, SiN_x, MgO_x, or any combination thereof.

13. The method of claim 12, wherein the second dielectric layer is selected from the group consisting of AlO_x, TaO_x, SiN_x, MgO_x, or any combination thereof.

14. The method of claim 7, wherein the removing of the first portion of the sensor stack comprises reactive ion etching, ion milling or the combination thereof.

15. The method of claim 14, wherein the removing of the second portion of the sensor stack comprises reactive ion etching, ion milling or combinations thereof.

16. The method of claim 15, wherein the removing of the third portion of the sensor stack comprises reactive ion etching, ion milling or combinations thereof.

17. The method of claim 7, further comprising planarizing a first top of the sensor stack after the depositing the first dielectric layer.

18. The method of claim 17, further comprising planarizing a second top of the sensor stack after the depositing the hard or soft bias layer.

19. A method of forming a magnetic head, comprising:

forming a sensor stack over a substrate wherein the sensor stack has at least a pinned layer, a non-magnetic layer disposed on the pinned layer, and a free layer disposed on the non-magnetic layer;

forming one or more channels within the sensor stack;

filling the one or more channels with a hard or soft bias material, wherein the hard or soft bias material has a substantially uniform thickness within the one or more channels; and

defining the pinned layer stripe height and the hard or soft bias layer in the same process step.

20. The method of claim 19, further comprising a barrier layer disposed within the one or more channels on the substrate, wherein the hard or soft bias layer is disposed on the barrier layer.

21. The method of claim 20, wherein the barrier layer comprises SiN, TaOx, AlOx, or SiOxNy, the hard bias layer comprises CoFe, CoPt, FePt, or CoPtCr, and the soft bias layer comprises NiFe, CoFe, NiFeMo, alloys of these compounds, or any combination thereof.