GLOBAL LOW POWER CAPTURE SCHEME FOR CORES

• US 20140189454A1
• Filed: 12/28/2012
• Published: 07/03/2014
• Est. Priority Date: 12/28/2012
• Status: Active Grant

• Current Assignee: NVIDIA Corporation
• Original Assignee: NVIDIA Corporation
• Inventors: Puvvada, Satya, Sonawane, Milind, Agarwal, Vishal, Sanghani, Amit D., Sinha, Anubhav
• Granted Patent: US 9,222,981 B2
• Time in Patent Office: Days
• US Class Current: 714/729
• CPC Class Codes: G01R 31/318544 Scanning methods, algorithms and patterns G01R31/3183 takes precedence
• CPC Class Codes: G01R 31/318575 Power distribution; Power saving

Abstract

A method for testing an integrated circuit to reduce peak power problems during scan capture mode is presented. The method comprises programming a respective duration of a first time window for each of a plurality of cores and a cache on the integrated circuit. It further comprises counting the number of pulses of a first clock signal during the first time window for each of the plurality of cores and the cache. Subsequently, the method comprises staggering capture pulses to the plurality of cores and the cache by generating pulses of a second clock signal for each of the plurality of cores and the cache during a respective second time window, wherein the number of pulses generated is based on the respective number of first clock signal pulses counted for each of the plurality of cores and the cache.

Claims

1. A method for testing an integrated circuit, said method comprising:

programming a respective duration of a first time window for each of a plurality of cores and a cache on the integrated circuit;

counting a number of pulses of a first clock signal during the first time window for each of the plurality of cores and the cache; and

staggering capture pulses to the plurality of cores and the cache by generating pulses of a second clock signal for each of the plurality of cores and the cache during a respective second time window, wherein a number of pulses generated is based on a respective number of first clock signal pulses counted for each of the plurality of cores and the cache.

2. The method of claim 1, further comprising pulsing each of the plurality of cores with the cache while staggering remaining cores in separate ATPG runs to obtain coverage for combinational paths between a respective core and the cache.

3. The method of claim 2, further comprising masking paths between the cache and the remaining cores.

4. The method of claim 1, further comprising dynamically obtaining coverage for substantially all combinational paths on the integrated circuit during a single ATPG run by pulsing a first subset of the plurality of cores and the cache together while staggering remaining cores.

5. The method of claim 4, wherein modules to be included in the first subset are dynamically determined, and wherein the modules can be comprised of cores and the cache.

6. The method of claim 5, wherein combinational paths between the modules in the first subset and the remaining cores is masked when the cores and the cache in the first subset are pulsed together.

7. The method of claim 1 wherein the integrated circuit is selected from the group comprising:

a graphics processor and a central processor.

8. The method of claim 1 wherein the respective duration of the first time window is programmable by a user.

9. A method for testing an integrated circuit, said method comprising:

programming a respective duration of a first time window for each of a plurality of modules on the integrated circuit, wherein the modules comprise cores and a cache;

counting a number of pulses of a first clock signal during the first time window for each of the plurality of modules; and

dynamically staggering capture pulses to a first subset of modules by generating pulses of a second clock signal for each of the plurality of cores and the cache during a respective second time window, wherein a number of pulses generated is based on the respective number of first clock signal pulses counted for each of the plurality of modules.

10. The method of claim 9 wherein a second subset of modules receives the pulses of the second clock signal simultaneously, wherein the second subset of modules comprises modules not included in the first subset.

11. The method of claim 10 wherein a value of a number of modules in the second subset is programmable.

12. A system for testing an integrated circuit, said system comprising:

a computer system comprising a tester processor, wherein said tester processor is communicatively coupled to a integrated circuit, wherein said integrated circuit comprises;

a plurality of cores and a cache;

an I/O port operable to program a respective duration of a first time window for each of the plurality of cores and the cache on the integrated circuit; and

a plurality of fast clock generating modules configured to;

count a number of pulses of a first clock signal during the first time window for each of the plurality of cores and the cache; and

stagger capture pulses to the plurality of cores and the cache by generating pulses of a second clock signal for each of the plurality of cores and the cache during a respective second time window, wherein a number of pulses generated is based on a respective number of first clock signal pulses counted for each of the plurality of cores and the cache.

13. The system of claim 12, wherein the plurality of fast clock generating modules are further configured to pulse each of the plurality of cores with the cache while staggering remaining cores during separate ATPG runs to obtain coverage for combinational paths between a respective core and the cache.

14. The system of claim 13, wherein the plurality of fast clock generating modules are further configured to mask paths between the cache and the remaining cores.

15. The system of claim 12, further comprising a dynamic capture clock staggering module configured to dynamically obtain coverage for substantially all combinational paths on the integrated circuit during a single ATPG run by pulsing a first subset of the plurality of cores and cache together while staggering remaining cores.

16. The system of claim 15, wherein a cache and cores to be included in the first subset is dynamically determined by the dynamic capture clock staggering module.

17. The system of claim 12, wherein the I/O port is a JTAG port operable to be programmed by a user.

18. The system of claim 12, wherein the integrated circuit is selected from the group comprising:

a graphics processor and a central processor.

19. The system of claim 12, wherein a number of capture pulses generated can be changed by altering the respective duration of the first time window for each of the plurality of cores and the cache.