SYSTEM AND METHOD FOR MULTICHANNEL CRYPTOGRAPHIC PROCESSING

• US 20140192975A1
• Filed: 10/17/2013
• Published: 07/10/2014
• Est. Priority Date: 10/17/2012
• Status: Active Grant

• Current Assignee: Synopsys Incorporated
• Original Assignee: Elliptic Technologies, Inc. (Synopsys Incorporated)
• Inventors: BORZA, Michael, HAMILTON, Neil, BOURDON, Franois
• Granted Patent: US 10,103,876 B2
• Time in Patent Office: Days
• US Class Current: 380/42
• CPC Class Codes: G06F 21/72 in cryptographic circuits
• CPC Class Codes: G06F 21/755 with measures against power attack
• CPC Class Codes: G06F 2221/2123 Dummy operation
• CPC Class Codes: H04L 9/003 for power analysis, e.g. differential power analysis [DPA] or simple power analysis [SPA]

Abstract

A processor is disclosed for ciphering of first data. The processor includes a key store and a first data store. In use the processor for ciphering the first data in accordance with a first cipher process and a first secret key to provide output data, during ciphering of the first data inserting within the cipher processor other data for ciphering in accordance with at least a portion of the first cipher process, the other data inserted within a sequence of cipher processor operations and scheduled for obfuscating the output data.

Claims

1. A cipher processor comprising:

a key store for storing a first secret key;

a first data store for storing at least a portion of first data; and

said cipher processor for ciphering the first data in accordance with a first cipher process and the first secret key to provide output data, during ciphering of the first data inserting within the cipher processor other data for ciphering in accordance with at least a portion of the first cipher process, the other data for being ciphered within a sequence of cipher processor operations and scheduled for obfuscating the output data.

2. A cipher processor according to claim 1 wherein during use the other data is dummy data.

3. A cipher processor according to claim 2 wherein during use the other data are inserted at one or more locations within the sequence of cipher processor operations to obfuscate operation of the cipher processor from side-channel attack.

4. A cipher processor according to claim 1 wherein during use the other data are inserted to make it difficult to determine by way of side-channel attack when initial and final rounds occur.

5. A cipher processor according to claim 1 wherein during use the other data is disposed within a sequence of the first data differently for different first data to make it difficult to determine by way of side-channel attack when within the sequence of cipher processor operations the first data are being inserted.

6. A method comprising:

providing a cipher processor for ciphering data provided thereto;

providing a first secret key;

providing first data to the cipher processor, the first data provided for being ciphered by the cipher processor with the first secret key;

providing a second secret key;

providing second data to the cipher processor, the second data provided for being ciphered by the cipher processor with the second secret key;

multiplexing the first ciphered data, the second ciphered data, and at least a dummy round to form a combined stream of data sequenced in a multiplexing order other than consistent between multiplexing operations; and

providing the multiplexing order to a demultiplexer for extracting the first ciphered data and the second ciphered data separately from the multiplexed data after ciphering thereof.

7. A method according to claim 6 wherein the multiplexing order is provided once determined during multiplexing.

8. A method according to claim 6 wherein the multiplexing order is determined by a multiplexer and by a demultiplexer from same known data.

9. A method according to claim 6 wherein the multiplexing order is determined by the multiplexer and by the demultiplexer from same predetermined data.

10. A method according to claim 6 comprising inserting within a stream of data for use within a cipher process a plurality of dummy rounds within a third stage thereof, a location of the dummy rounds varying from one third stage to another third stage.

11. A method comprising:

providing a first secret key;

providing a cipher processor;

providing within the cipher processor a first sequence of cipher processor operations for ciphering a first stream of data to form ciphered first data;

providing within the cipher processor a second sequence of cipher processor operations for ciphering a second stream of data;

multiplexing the first sequence of cipher processor operations and the second sequence of cipher processor operations to form a combined stream of cipher processor operations, the combined stream of cipher processor operations sequenced in a manner other than consistent between different first sequences of cipher processor operations and second sequences of cipher processor operations;

ciphering by the cipher processor the first stream of data in accordance with an expanded key set based on the first secret key by performing the first sequence of cipher processor operations thereon; and

providing the ciphered first data in one of ciphered and plain text form at an output port of the cipher processor.

12. A method according to claim 11 wherein the second stream of data comprises dummy data for forming dummy rounds.

13. A method according to claim 12 comprising:

providing a second secret key;

ciphering by the cipher processor the second stream of data in accordance with an expanded key set based on the second secret key by performing the second sequence of cipher processor operations thereon to form ciphered second data; and

providing the ciphered second data in one of ciphered and plain text form at an output port of the cipher processor.

14. A method according to claim 13 wherein the second sequence of cipher processor operations is multiplexed with the first sequence of cipher processor operations in a pseudo random fashion.

15. A method according to claim 14 wherein the pseudo random fashion is deterministic by the cipher processor but is other than deterministic from other than the cipher processor.

16. A method according to claim 12 wherein the second sequence of cipher processor operations is multiplexed with the first sequence of cipher processor operations in a pseudo random fashion.

17. A method according to claim 16 wherein the pseudo random fashion is deterministic by the cipher processor but is other than deterministic from other than the cipher processor.

18. A method as defined in claim 11 wherein ciphering of the second stream of data is performed in dependence upon a different secret key.

19. A method as defined in claim 11 wherein ciphering of the second stream of data is performed in dependence upon a same secret key.

20. A cipher processor comprising:

a first key store for storing a first secret key therein;

a first data store for storing first data;

a circuit for performing a first sequence of cipher operations for ciphering of the first data and a second sequence of cipher operations for ciphering second other data;

a scheduler for determining a known manner for intermixing the first data and the second other data, the known manner other than consistent between different first data and second other data; and

a multiplexer for multiplexing the first sequence and the second sequence of cipher operations in accordance with the known manner.

21. A cipher processor as defined in claim 20 wherein the second other data is other than retrieved from a data store within the cipher processor.

22. A cipher processor as defined in claim 20 wherein in use the second other data is dummy data.

23. A cipher processor as defined in claim 20 comprising:

a second key store for storing a second secret key therein,

wherein the second other data comprises a separate stream of data for being ciphered by the cipher processor in dependence upon the second secret key.