FOCAL PLANE ARRAY PROCESSING METHOD AND APPARATUS

• US 20140197303A1
• Filed: 03/21/2014
• Published: 07/17/2014
• Est. Priority Date: 10/27/2006
• Status: Active Grant

• Current Assignee: Massachusetts Institute of Technology
• Original Assignee: Brian Tyrrell, Curtis Colonero, Daniel Mooney, James Wey, Kenneth Schultz, Lawrence Candell, Michael Kelly, Robert Berger
• Inventors: KELLY, MICHAEL, TYRRELL, BRIAN, COLONERO, CURTIS, BERGER, ROBERT, SCHULTZ, KENNETH, WEY, JAMES, MOONEY, DANIEL, CANDELL, LAWRENCE
• Granted Patent: US 9,491,389 B2
• Time in Patent Office: Days
• US Class Current: 250/208.1
• CPC Class Codes: G06F 21/602 Providing cryptographic facilities or services
• CPC Class Codes: G09C 1/00 Apparatus or methods whereby a given sequence of signs, e.g. an intelligible text, is transformed into an unintelligible sequence of signs by transposing the signs or groups of signs or by replacing them by others according to a predetermined system cryptographic typewriters G09C3/00
• CPC Class Codes: G11B 20/00086 Circuits for prevention of unauthorised reproduction or copying, e.g. piracy indicating unauthorised use of record carriers in general G11B23/28; scrambling for television signal recording H04N5/913; network architectures or network protocols for network security H04L63/00; cryptographic mechanisms or cryptographic arrangements for secret or secure communication H04L9/00
• CPC Class Codes: G11B 20/0021 involving encryption or decryption of contents recorded on or reproduced from a record carrier
• CPC Class Codes: H04L 2209/12 Details relating to cryptographic hardware or logic circuitry
• CPC Class Codes: H04L 2209/805 Lightweight hardware, e.g. radio-frequency identification [RFID] or sensor
• CPC Class Codes: H04L 9/0631 Substitution permutation network [SPN], i.e. cipher composed of a number of stages or rounds each involving linear and nonlinear transformations, e.g. AES algorithms
• CPC Class Codes: H04L 9/0637 Modes of operation, e.g. cipher block chaining [CBC], electronic codebook [ECB] or Galois/counter mode [GCM]
• CPC Class Codes: H04L 9/12 Transmitting and receiving encryption devices synchronised or initially set up in a particular manner
• CPC Class Codes: H04N 2005/91364 the video signal being scrambled
• CPC Class Codes: H04N 21/4223 Cameras H04N23/00 takes precedence
• CPC Class Codes: H04N 21/4408 involving video stream encryption, e.g. re-encrypting a decrypted video stream for redistribution in a home network
• CPC Class Codes: H04N 25/75 Circuitry for providing, modifying or processing image signals from the pixel array
• CPC Class Codes: H04N 5/33 Transforming infrared radiation cameras or camera modules for generating image signals from infrared radiation H04N23/20; circuitry of SSIS for transforming infrared radiation into image signals H04N25/20
• CPC Class Codes: H04N 5/772 the recording apparatus and the television camera being placed in the same enclosure
• CPC Class Codes: H04N 5/913 for scrambling ; for copy protection

Abstract

A digital focal plane array includes an all-digital readout integrated circuit in combination with a detector array. The readout circuit includes unit cell electronics, orthogonal transfer structures, and data handling structures. The unit cell electronics include an analog to digital converter. Orthogonal transfer structures enable the orthogonal transfer of data among the unit cells. Data handling structures may be configured to operate the digital focal plane array as a data encryptor/decipherer. Data encrypted and deciphered by the digital focal plane array need not be image data.

Claims

1. An apparatus comprising:

a two-dimensional array of photodetectors; and

a two-dimensional array of analog-to-digital converters (ADCs), wherein at least one ADC in the two-dimensional array of ADCs comprises;

a capacitor operably coupled to a photodetector in the two-dimensional array of photodetectors to integrate current from the photo detector;

a comparator operably coupled to the capacitor to generate a latch signal when a voltage across the capacitor reaches a reference voltage; and

a voltage source operably coupled to the capacitor to charge the capacitor to a reset voltage between ground and the reference voltage after the comparator generates the latch signal.

2. The apparatus of claim 1, wherein a frequency of the latch signal is independent of a capacitance of the capacitor and of the reference voltage.

3. The apparatus of claim 1, further comprising a switch to disconnect the voltage source from the capacitor while the capacitor integrates the current from the photodetector.

4. The apparatus of claim 1, further comprising a transistor that operably couples the photodetector to the capacitor.

5. The apparatus of claim 1, wherein the at least one ADC further comprises a counter to latch a count value based on the latch signal.

6. The apparatus of claim 5, further comprising a clock to generate a clock signal that determines a count rate of the counter.

7. The apparatus of claim 5, wherein the counter is a modulo M counter.

8. An apparatus comprising:

a two-dimensional array of photodetectors; and

a two-dimensional array of analog-to-digital converters (ADCs) operably coupled to the two-dimensional array of photodetectors, wherein at least one ADC in the two-dimensional array of ADCs comprises;

a modulo M counter to store a count value representing a current generated by a corresponding photodetector in the two-dimensional array of photodetectors.

9. The apparatus of claim 8, wherein M is the product of two prime numbers.

10. The apparatus of claim 8, wherein the modulo M counter is a bidirectional counter.

11. The apparatus of claim 8, wherein the at least one ADC further comprises a capacitor to integrate the current generated by the corresponding photodetector.

12. The apparatus of claim 11, wherein the at least one ADC further comprises at least one of a voltage-to-frequency converter and a comparator to convert a voltage across the capacitor to a signal that increments or decrements the count value stored in the modulo M counter.