Reset Supervisor

• US 20140201570A1
• Filed: 01/16/2013
• Published: 07/17/2014
• Est. Priority Date: 01/16/2013
• Status: Active Grant

• Current Assignee: Nike, Inc.
• Original Assignee: Nike, Inc.
• Inventors: Bielman, James, Cummings, Kate, Lowe, Edward Stephen Jr.
• Granted Patent: US 9,170,872 B2
• Time in Patent Office: Days
• US Class Current: 714/23
• CPC Class Codes: G06F 1/24 Resetting means
• CPC Class Codes: G06F 11/0724 in a multiprocessor or a multi-core unit multiprocessors per se G06F15/80
• CPC Class Codes: G06F 11/079 Root cause analysis, i.e. error or fault diagnosis in a hardware test environment G06F11/22; in a software test environment G06F11/36
• CPC Class Codes: G06F 11/0793 Remedial or corrective actions recovery from an exception in an instruction pipeline G06F9/3861; by retry G06F11/1402; for recovering from a failure of a protocol instance or entity H04L69/40
• CPC Class Codes: G06F 11/1441 Resetting or repowering
• CPC Class Codes: G06F 13/385 for adaptation of a particular data processing system to different peripheral devices
• CPC Class Codes: G06F 8/65 Updates security arrangements therefor G06F21/57
• CPC Class Codes: G06F 9/4411 Configuring for operating with peripheral devices; Loading of device drivers

Abstract

Multiple processor systems are provided. A first processor is configured to monitor the state of at least one other processor by comparing received signals. When the first processor determines that another processor needs to be reset, the first processor provides a reset signal to a reset pin of the processor that needs to be reset. The first processor may reset itself after providing the reset signal.

Claims

1. A method comprising:

(a) receiving an input signal at a first processor and at a second processor;

(b) at the first processor processing the input signal to generate an output signal;

(c) transmitting the output signal from the first processor to the second processor; and

(d) at the second processor comparing the input signal to the output signal and determining that an error exists when the input signal does not correspond to the output signal.

2. The method of claim 1, wherein the input signal comprises a power signal.

3. The method of claim 2, wherein the power signal comprises a USB VBUS signal.

4. The method of claim 1, further including transmitting the input signal from a wireless receiver to the first processor and the second processor.

5. The method of claim 1, wherein the input signals has a first voltage level and the output signal has a second voltage.

6. The method of claim 5, wherein (d) comprises comparing the first voltage level to the second voltage level.

7. The method of claim 1, wherein (d) comprises comparing timing information of the input signal to timing information of the output signal.

8. The method of claim 1, further comprising:

(e) when an error exists in (d) transmitting a reset signal from the second processor to the first processor to reset the first processor.

9. The method of claim 8, further comprising:

(f) receiving the reset signal at the first processor; and

(g) in response to (f) loading firmware into the first processor.

10. The method of claim 8, further comprising:

(f) resetting the first processor.

11. The method of claim 8, further comprising:

(f) after (e), resetting the second processor.

12. The method of claim 1, further comprising

(e) receiving a user input at the second processor;

and

(f) when an error exists in (d) transmitting a reset signal from the second processor to the first processor to reset the first processor in a manner determined by the user input.

13. The method of claim 12, wherein the user input comprises a selection of a hard reset or a soft reset.

14. The method of claim 1, wherein (d) comprises determining that an error exists when the output signal has a voltage level of 0.

15. A method of monitoring and resetting a processor, the method comprising:

(a) receiving from a port at least one bus signal at a first processor and at a second processor;

(b) at the second processor determining that an error exist when the first processor does not provide the at least one bus signal to the second processor; and

(c) when an error exists in (b), transmitting a reset signal from the second processor to the first processor.

16. The method of claim 15, wherein the at least one bus signal comprises at least one USB signal.

17. The method of claim 16, wherein the at least one USB signal comprises a VBUS signal.

18. The method of claim 16, wherein the at least one USB signal comprises two USB signals.

19. A tangible computer-readable medium that contains computer-executable instructions that when executed cause a processor to perform the steps comprising:

(a) receiving from a port at least one bus signal;

(b) receiving from another processor at least one bus signal;

(c) determining that an error condition exists when the bus signals received in (a) and in (b) do not correspond; and

(d) when an error condition exists, transmitting a reset signal to said another processor.

20. The tangible computer-readable medium of claim 19, wherein the at least one bus signal in (b) comprises a USB VBUS signal.