3-D Memory Arrays

• US 20140217488A1
• Filed: 02/05/2013
• Published: 08/07/2014
• Est. Priority Date: 02/05/2013
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Thimmegowda, Deepak, Cleereman, Brian, Hasnat, Khaled
• Granted Patent: US 9,219,070 B2
• Time in Patent Office: Days
• US Class Current: 257/314
• CPC Class Codes: H01L 27/0207 Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
• CPC Class Codes: H01L 29/7889 Vertical transistors, i.e. transistors having source and drain not in the same horizontal plane
• CPC Class Codes: H01L 29/7926 Vertical transistors, i.e. transistors having source and drain not in the same horizontal plane
• CPC Class Codes: H10B 41/10 characterised by the top-view layout
• CPC Class Codes: H10B 41/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 43/10 characterised by the top-view layout
• CPC Class Codes: H10B 43/27 the channels comprising vertical portions, e.g. U-shaped channels

Abstract

A 3-D memory array comprises a plurality of elevationally extending strings of memory cells. An array of select devices is elevationally over and individually coupling with individual of the strings. The select devices individually comprise a channel, gate dielectric proximate the channel, and gate material proximate the gate dielectric. The individual channels are spaced from one another. The gate material comprises a plurality of gate lines running along columns of the spaced channels elevationally over the strings. Dielectric material is laterally between immediately adjacent of the gate lines. The dielectric material and the gate lines have longitudinally non-linear edges at an interface relative one another. Additional embodiments are disclosed.

Claims

1. A 3-D memory array, comprising:

a plurality of elevationally extending strings of memory cells;

an array of select devices elevationally over and individually coupling with individual of the strings;

the select devices individually comprising a channel, gate dielectric proximate the channel, and gate material proximate the gate dielectric;

the individual channels being spaced from one another;

the gate material comprising a plurality of gate lines running along columns of the spaced channels elevationally over the strings; and

dielectric material laterally between immediately adjacent of the gate lines, the dielectric material and the gate lines having longitudinally non-linear edges at an interface relative one another.

2. The 3-D memory array of claim 1 wherein the dielectric material and the gate lines having longitudinally curvilinear edges at the interface.

3. The 3-D memory array of claim 1 wherein the channels in immediately adjacent of the columns between the immediately adjacent gate lines are longitudinally staggered relative one another.

4. The 3-D memory array of claim 3 wherein the channels of the immediately adjacent columns between the immediately adjacent gate lines are longitudinally equidistantly staggered relative one another.

5. The 3-D memory array of claim 1 wherein the channels of all immediately adjacent of the columns are longitudinally staggered relative one another.

6. The 3-D memory array of claim 3 wherein the channels of the immediately adjacent columns between the immediately adjacent gate lines are longitudinally equidistantly staggered relative one another.

7. The 3-D memory array of claim 1 comprising multiple columns of spaced channels in individual of the gate lines.

8. The 3-D memory array of claim 1 wherein the memory cells are serially coupled within the individual strings, the strings individually comprising an active area pillar extending through elevationally inner tiers, the inner tiers individually comprising charge storage structures adjacent the pillars and access lines adjacent the charge storage structures, the select devices comprising select gate drains (SGD'"'"'s).

9. The 3-D memory array of claim 1 wherein the select devices across the dielectric material have pitch equal to channel width plus twice gate dielectric width plus gate material width between the gate dielectric and the dielectric material plus dielectric material width.

10. The 3-D memory array of claim 1 wherein the channels in the columns with respect to immediately adjacent of the gate lines are longitudinally equidistantly staggered relative one another;

and

the select devices across the dielectric material have pitch P equal to

11. The 3-D memory array of claim 1 wherein individual of the gate lines comprise multiple columns of spaced channels individually surrounded by material of the individual gate line;

and

pitch of the select devices across immediately adjacent of the gate lines is less than pitch of the select devices within individual of the gate lines.

12. The 3-D memory array of claim 1 wherein individual of the gate lines comprise multiple columns of spaced channels individually surrounded by material of the individual gate line;

and

pitch of the select devices across immediately adjacent of the gate lines is greater than pitch of the select devices within individual of the gate lines.

13. A 3-D memory array, comprising:

a plurality of elevationally extending strings of memory cells; and

an array of select devices elevationally over and individually coupling with individual of the strings, the select devices comprising nested longitudinally curvilinear gate lines laterally separated by dielectric material.

14. The 3-D memory array of claim 13 wherein the select devices comprise channels that are individually spaced from one another along a column in individual of the gate lines, the channels of immediately adjacent of the columns between immediately adjacent of the gate lines being longitudinally staggered relative one another.

15. The 3-D memory array of claim 13 wherein the memory cells are serially coupled within the individual strings, the strings individually comprising an active area pillar extending through elevationally inner tiers, the inner tiers individually comprising charge storage structures adjacent the pillars and access lines adjacent the charge storage structures.

16. The 3-D memory array of claim 15 wherein the select devices comprise select gate drains (SGD'"'"'s).

17. A 3-D memory array, comprising:

a plurality of elevationally extending strings of memory cells;

an array of select devices elevationally over and individually coupling with individual of the strings, the select devices comprising gate lines laterally separated by dielectric material; and

the select devices across the dielectric material have pitch equal to select device channel width plus twice gate dielectric width plus gate line material width between the gate dielectric and the dielectric material plus dielectric material width.

18. The 3-D memory array of claim 17 wherein the select devices comprise a column of channels within individual of the gate lines, the channels in the columns with respect to immediately adjacent of the gate lines being longitudinally equidistantly staggered relative one another;

and

the select devices across the dielectric material have pitch P equal to

19. The 3-D memory array of claim 17 wherein individual of the gate lines comprise multiple columns of spaced select device channels individually surrounded by material of the individual gate line;

and

pitch of the select devices across immediately adjacent of the gate lines being less than pitch of the select devices within individual of the gate lines.

20. The 3-D memory array of claim 19 wherein the channels in the columns with respect to immediately adjacent of the gate lines are longitudinally equidistantly staggered relative one another;

and

the select devices across the dielectric material have pitch P equal to

21. The 3-D memory array of claim 20 wherein the channels of all immediately adjacent of the columns are longitudinally staggered relative one another.

22. The 3-D memory array of claim 17 wherein the memory cells are serially coupled within the individual strings, the strings individually comprising an active area pillar extending through elevationally inner tiers, the inner tiers individually comprising charge storage structures adjacent the pillars and access lines adjacent the charge storage structures, the select devices comprising select gate drains (SGD'"'"'s)

23. A 3-D memory array, comprising:

a plurality of elevationally extending strings of memory cells;

an array of select devices elevationally over and individually coupling with individual of the strings, the select devices comprising gate lines laterally separated by dielectric material, the select devices comprising a column of spaced channels within individual of the gate lines, the channels in the columns with respect to immediately adjacent of the gate lines being longitudinally equidistantly staggered relative one another; and

the select devices across the dielectric material have pitch P equal to

24. The 3-D memory array of claim 23 wherein individual of the gate lines comprise multiple columns of spaced channels individually surrounded by material of the individual gate line;

and

pitch of the select devices across immediately adjacent of the gate lines being less than pitch of the select devices within individual of the gate lines.

25. The 3-D memory array of claim 23 wherein the memory cells are serially coupled within the individual strings, the strings individually comprising an active area pillar extending through elevationally inner tiers, the inner tiers individually comprising charge storage structures adjacent the pillars and access lines adjacent the charge storage structures, the select devices comprising select gate drains (SGD'"'"'s).

26. A 3-D memory array, comprising:

a plurality of elevationally extending strings of memory cells;

an array of select devices elevationally over and individually coupling with individual of the strings, the select devices comprising gate lines laterally separated by dielectric material, individual of the gate lines comprising multiple columns of spaced select device channels individually surrounded by material of the individual gate line; and

pitch of the select devices across immediately adjacent of the gate lines being less than pitch of the select devices within individual of the gate lines.

27. The 3-D memory array of claim 26 wherein the memory cells are serially coupled within the individual strings, the strings individually comprising an active area pillar extending through elevationally inner tiers, the inner tiers individually comprising charge storage structures adjacent the pillars and access lines adjacent the charge storage structures, the select devices comprising select gate drains (SGD'"'"'s).

28. A 3-D memory array, comprising:

a plurality of serially-coupled and elevationally extending strings of memory cells, the strings individually comprising an active area pillar extending through elevationally inner tiers, the inner tiers individually comprising charge storage structures adjacent the pillars and access lines adjacent the charge storage structures;

an elevationally outer tier comprising an array of select gate drains (SGD'"'"'s) that individually couple with the individual strings;

the SGD'"'"'s individually comprising a channel pillar elevationally over and coupled with one of the active area pillars, gate dielectric surrounding the channel pillar, and gate material surrounding the gate dielectric;

the gate material comprising a plurality of SGD gate lines in the outer tier running along columns of the channel pillars;

the channel pillars in immediately adjacent of the columns between the immediately adjacent gate lines being longitudinally equidistantly staggered relative one another; and

dielectric material in the outer tier laterally separating immediately adjacent of the gate lines, the dielectric material and the gate lines having longitudinally curvilinear edges at an interface relative one another.

29. The 3-D memory array of claim 28 comprising a tier elevationally inward of the inner tiers, the inward tier comprising an array of select gate sources (SGS'"'"'s) that individually couple with the individual strings.

30. The 3-D memory array of claim 28 wherein the channel pillars of all immediately adjacent of the columns are longitudinally staggered relative one another.

31. The 3-D memory array of claim 28 wherein the SGD'"'"'s across the dielectric material have pitch equal to channel pillar width plus twice gate dielectric width plus gate material width between the gate dielectric and the dielectric material plus dielectric material width.

32. The 3-D memory array of claim 28 wherein the SGD'"'"'s across the dielectric material have pitch P equal to

33. The 3-D memory array of claim 28 wherein individual of the gate lines comprise multiple columns of spaced select device channel pillars individually surrounded by material of the individual gate line;

and

pitch of the SGD'"'"'s across immediately adjacent of the gate lines is less than pitch of the SGD'"'"'s within the individual gate lines.

34. The 3-D memory array of claim 28 wherein individual of the gate lines comprise multiple columns of spaced channels individually surrounded by material of the individual gate line;

and

pitch of the select devices across immediately adjacent of the gate lines is greater than pitch of the select devices within individual of the gate lines.