SMART BRIDGE FOR MEMORY CORE

• US 20140219022A1
• Filed: 04/07/2014
• Published: 08/07/2014
• Est. Priority Date: 06/30/2011
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: Sandisk Technologies Incorporated (Western Digital Corporation)
• Inventors: D'ABREU, MANUEL ANTONIO, SKALA, STEPHEN, PANTELAKIS, DIMITRIS, NAIR, RADHAKRISHNAN, PANCHOLI, DEEPAK
• Granted Patent: US 9,177,612 B2
• Time in Patent Office: Days
• US Class Current: 365/185.08
• CPC Class Codes: G06F 11/1048 using arrangements adapted for a specific error detection or correction feature
• CPC Class Codes: G06F 11/1068 in sector programmable memories, e.g. flash disk G06F11/1072 takes precedence
• CPC Class Codes: G06F 11/1072 in multilevel memories
• CPC Class Codes: G06F 13/1668 Details of memory controller
• CPC Class Codes: G11C 14/0063 and the nonvolatile element is an EEPROM element, e.g. a floating gate or MNOS transistor
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 2029/0411 Online error correction
• CPC Class Codes: G11C 29/04 Detection or location of defective memory elements , e.g. cell constructio details, timing of test signals
• CPC Class Codes: G11C 5/02 Disposition of storage elements, e.g. in the form of a matrix array
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

An apparatus includes a semiconductor device that includes a multi-ported three-dimensional (3D) memory. The multi-ported 3D memory includes multiple memory cells arranged in multiple physical levels above a substrate. The multi-ported 3D memory includes circuitry associated with operation of the multiple memory cells.

Claims

1. An apparatus comprising:

a semiconductor device including a multi-ported three-dimensional (3D) memory that includes multiple memory cells arranged in multiple physical levels above a substrate,

wherein the multi-ported 3D memory includes circuitry associated with operation of the multiple memory cells.

2. The apparatus of claim 1, further comprising a second semiconductor device coupled to the multi-ported 3D memory, the second semiconductor device including a multi-ported static random access memory (SRAM).

3. The apparatus of claim 2, wherein the second semiconductor device is configured to cache data at the multi-ported SRAM and to initiate a data store operation at the multi-ported 3D memory by sending the cached data and instructions to the multi-ported 3D memory via a multi-ported memory interface.

4. The apparatus of claim 2, wherein the second semiconductor device includes periphery circuitry corresponding to the multi-ported 3D memory and periphery circuitry corresponding to a second memory, and wherein the second semiconductor device is responsive to a memory controller and configured to initiate a first memory operation at the multi-ported 3D memory and a second memory operation at the second memory.

5. The apparatus of claim 1, wherein the substrate is a silicon substrate.

6. The apparatus of claim 1, wherein the circuitry associated with operation of the multiple memory cells is configured to be responsive to a write instruction to store data into memory cells of the 3D memory and to be responsive to a read instruction to read data from the memory cells of the 3D memory.

7. An apparatus comprising:

a first memory die comprising a first three-dimensional (3D) memory that includes multiple memory cells arranged in multiple physical levels above a substrate, wherein the first 3D memory includes circuitry associated with operation of the multiple memory cells;

a second memory die comprising a second memory; and

a periphery die coupled to the first memory die and to the second memory die, wherein the periphery die comprises periphery circuitry corresponding to the first 3D memory and periphery circuitry corresponding to the second memory, and wherein the periphery die is responsive to a memory controller and configured to initiate a first memory operation at the first 3D memory and a second memory operation at the second memory.

8. The apparatus of claim 7, wherein the 3D memory is a multi-ported 3D memory.

9. The apparatus of claim 7, wherein the periphery die is configured to perform the first memory operation substantially concurrently with performing the second memory operation.

10. The apparatus of claim 7, wherein the periphery die is configured to receive data from the memory controller, wherein the first memory operation includes storing a first portion of the data to the first 3D memory, and wherein the second memory operation includes storing a second portion of the data to the second memory.

11. The apparatus of claim 7, wherein the substrate is a silicon substrate.

12. The apparatus of claim 7, wherein the circuitry associated with operation of the multiple memory cells is configured to be responsive to a write instruction to store data into memory cells of the 3D memory and to be responsive to a read instruction to read data from the memory cells of the 3D memory.

13. A method comprising:

receiving data at a semiconductor device including a multi-ported three-dimensional (3D) memory that includes multiple memory cells arranged in multiple physical levels above a substrate, wherein the multi-ported 3D memory includes circuitry associated with operation of the multiple memory cells; and

storing the data in the multi-ported 3D memory.

14. The method of claim 13, wherein the data is received from a multi-ported static random access memory (SRAM) of a second semiconductor device.

15. The method of claim 13, wherein the substrate is a silicon substrate.

16. The method of claim 13, wherein the circuitry associated with operation of the multiple memory cells is configured to be responsive to a write instruction to store data into memory cells of the 3D memory and to be responsive to a read instruction to read data from the memory cells of the 3D memory.

17. A method comprising:

receiving a request at a periphery die, the request received from a memory controller coupled to the periphery die; and

in response to the request;

initiating a first memory operation at a first memory die comprising a first three-dimensional (3D) memory that includes multiple memory cells arranged in multiple physical levels above a substrate, wherein the first 3D memory includes circuitry associated with operation of the multiple memory cells; and

initiating a second memory operation at a second memory die comprising a second memory,

wherein the periphery die comprises periphery circuitry corresponding to the first 3D memory and periphery circuitry corresponding to the second memory.

18. The method of claim 17, wherein the periphery die is configured to perform the first memory operation substantially concurrently with performing the second memory operation.

19. The method of claim 17, wherein the substrate is a silicon substrate.

20. The method of claim 17, wherein the circuitry associated with operation of the multiple memory cells is configured to be responsive to a write instruction to store data into memory cells of the 3D memory and to be responsive to a read instruction to read data from the memory cells of the 3D memory.