LATERAL EXTENDED DRAIN METAL OXIDE SEMICONDUCTOR FIELD EFFECT TRANSISTOR (LEDMOSFET) WITH TAPERED AIRGAP FIELD PLATES

• US 20140225186A1
• Filed: 02/08/2013
• Published: 08/14/2014
• Est. Priority Date: 02/08/2013
• Status: Active Grant

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: International Business Machines Corporation
• Inventors: Abou-Khalil, Michel J., Letavic, Theodore J., Luce, Stephen E., Stamper, Anthony K.
• Granted Patent: US 9,245,960 B2
• Time in Patent Office: Days
• US Class Current: 257/330
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/66704 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/66712 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/7824 with a substrate comprising an insulating layer, e.g. SOI-LDMOS transistors
• CPC Class Codes: H01L 29/7825 with trench gate electrode trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

Disclosed are embodiments of a lateral, extended drain, metal oxide semiconductor, field effect transistor (LEDMOSFET) having tapered dielectric field plates positioned laterally between conductive field plates and opposing sides of a drain drift region of the LEDMOSFET. Each dielectric field plate comprises, in whole or in part, an airgap. These field plates form plate capacitors that can create an essentially uniform horizontal electric field profile within the drain drift region so that the LEDMOSFET can exhibit a specific, relatively high, breakdown voltage (Vb). Tapered dielectric field plates that incorporate airgaps provide for better control over the creation of the uniform horizontal electric field profile within the drain drift region, as compared to tapered dielectric field plates without such airgaps and, thereby ensure that the LEDMOSFET exhibits the specific, relatively high, Vb desired. Also disclosed herein are embodiments of a method of forming such an LEDMOSFET.

Claims

1. A field effect transistor comprising:

a semiconductor body having opposing sidewalls, a first end and a second end opposite said first end, said semiconductor body comprising;

a source region at said first end;

a drain region at said second end;

a channel region adjacent to said source region; and

a drain drift region between said channel region and said drain region;

dielectric field plates adjacent to said opposing sidewalls at said drain drift region; and

conductive field plates adjacent to said dielectric field plates,

each dielectric field plate being positioned laterally between said drain drift region and a conductive field plate, having a width that increases along a length of said drain drift region from said channel region to said drain region, and comprising a cavity filled with any one of air and gas.

2. The field effect transistor of claim 1, said cavity extending vertically to at least a top surface of an isolation layer below said semiconductor body and further having an essentially triangular shape defined by vertical surfaces of said semiconductor body at said drain drift region, of said conductive field plate and of an isolation region.

3. The field effect transistor of claim 2, wherein, within said cavity, said top surface of said isolation layer and said vertical surfaces of said semiconductor body, said conductive field plate and said isolation region are lined with a dielectric liner.

4. The field effect transistor of claim 1, said cavity having an essentially triangular shape such that said width increases linearly along said length of said drain drift region from said channel region to said drain region.

5. The field effect transistor of claim 1, further comprising a dielectric cap layer covering said cavity.

6. The field effect transistor of claim 1, said drain drift region having an essentially uniform horizontal electric field profile from said channel region to said drain region and said dielectric field plates having predefined dimensions so that said field effect transistor has a specific drain-to-body breakdown voltage.

7. The field effect transistor of claim 1, each conductive field plate comprising one of a discrete semiconductor shape, a discrete metal shape, and an extension of a gate structure traversing said channel region.

8. A field effect transistor comprising:

a semiconductor body having opposing sidewalls, a first end and a second end opposite said first end, said semiconductor body comprising;

a source region at said first end;

a drain region at said second end;

a channel region adjacent to said source region; and

a drain drift region between said channel region and said drain region;

dielectric field plates adjacent to said opposing sidewalls at said drain drift region; and

conductive field plates adjacent to said dielectric field plates,

each dielectric field plate being positioned laterally between said drain drift region and a conductive field plate, having a width that increases along a length of said drain drift region from said channel region to said drain region, and comprising;

a portion of an isolation region between said semiconductor body and said conductive field plate; and

a cavity contained within said portion of said isolation region.

9. The field effect transistor of claim 8, each dielectric field plate further comprising a dielectric cap layer covering said cavity.

10. The field effect transistor of claim 8, said portion of said isolation region having an essentially triangular shape such that said width increases linearly along said length of said drain drift region from said channel region to said drain region.

11. The field effect transistor of claim 10, said cavity having a smaller triangular shape than said portion of said isolation region.

12. The field effect transistor of claim 8, said drain drift region having an essentially uniform horizontal electric field profile from said channel region to said drain region and said dielectric field plates having predefined dimensions so that said field effect transistor has a specific drain-to-body breakdown voltage.

13. The field effect transistor of claim 8, each conductive field plate comprising one of a discrete semiconductor shape, a discrete metal shape, and an extension of a gate structure traversing said channel region.

14. A method of forming a field effect transistor, said method comprising:

forming a semiconductor body having opposing sidewalls, a first end and a second end opposite said first end, said semiconductor body further having the following regions;

a source region at said first end;

a drain region at said second end;

a channel region adjacent to said source region; and

a drain drift region between said channel region and said drain region; and

forming dielectric field plates adjacent to said opposing sidewalls at said drain drift region and conductive field plates adjacent to said dielectric field plates such that each dielectric field plate is positioned laterally between said drain drift region and a conductive field plate, has a width that increases along a length of said drain drift region from said channel region to said drain region, and comprises a cavity filled with any one of air and gas.

15. The method of claim 14, said conductive field plates being formed such that each conductive plate comprises any one of a discrete semiconductor shape, a discrete metal shape, and an extension of a gate structure traversing said channel region.

16. The method of claim 14, further comprising providing a semiconductor layer and forming an isolation region so as to define a cross shape in said semiconductor layer,

said forming of said semiconductor body and said forming of said dielectric field plates and said conductive field plates comprising:

forming trenches in said cross shape so as to define a rectangular shape for said semiconductor body and two discrete shapes on opposite sides of said rectangular shape for said conductive field plates;

forming a degradable sacrificial layer in said trenches;

forming a dielectric cap layer on said degradable sacrificial layer; and

performing a process to degrade said degradable sacrificial layer to form cavities for said dielectric field plates between said conductive field plates and said semiconductor body.

17. The method of claim 16, before said forming of said degradable sacrificial layer in said trenches, lining said trenches with a dielectric liner.

18. The method of claim 16, said trenches having an essentially triangular shape such that said width of said dielectric field plates increases linearly along said length of said drain drift region from said channel region to said drain region.

19. The method of claim 14, further comprising predefining dimensions of said dielectric field plates so that said drain drift region has an essentially uniform horizontal electric field profile from said channel region to said drain region and so that said field effect transistor has a specific drain-to-body breakdown voltage.

20. A method of forming a field effect transistor, said method comprising:

forming a semiconductor body having opposing sidewalls, a first end and a second end opposite said first end, said semiconductor body further having the following regions;

a source region at said first end;

a drain region at said second end;

a channel region adjacent to said source region; and

a drain drift region between said channel region and said drain region; and

forming dielectric field plates adjacent to said opposing sidewalls at said drain drift region and conductive field plates adjacent to said dielectric field plates such that each dielectric field plate is positioned laterally between said drain drift region and a conductive field plate, has a width that increases along a length of said drain drift region from said channel region to said drain region, and comprises;

a portion of an isolation region between said semiconductor body and said conductive field plate; and

a cavity contained within said portion of said isolation region.

21. The method of claim 20, said conductive field plates being formed such that each conductive plate comprises any one of a discrete semiconductor shape, a discrete metal shape, and an extension of a gate structure traversing said channel region.

22. The method of claim 20, further comprising providing a semiconductor layer, said forming of said semiconductor body and said forming of said dielectric field plates and said conductive field plates comprising:

forming an isolation region in said semiconductor layer so as to define a rectangular semiconductor shape for said semiconductor body and two discrete semiconductor shapes on said opposing sides of said semiconductor body for said conductive field plates, said conductive field plates being separated from said opposing sides of said semiconductor body at said drain drift region by portions of said isolation region;

forming trenches in said portions of said isolation region between said semiconductor body and said conductive field plates;

forming a degradable sacrificial layer in said trenches;

forming a dielectric layer on said degradable sacrificial layer; and

performing a process to degrade said degradable sacrificial layer to form cavities for said dielectric field plates.

23. The method of claim 22, said isolation region being formed such that said portion of said isolation region between said opposing sides of said semiconductor body at said drain drift region and said conductive field plates has an essentially triangular shape and, thereby such that said width of each of said dielectric field plates increases linearly along said length of said drain drift region from said channel region to said drain region.

24. The method of claim 23, each trench having a smaller essentially triangular shape than said portion of said isolation region.

25. The method of claim 20, further comprising predefining dimensions of said dielectric field plates so that said drain drift region has an essentially uniform horizontal electric field profile from said channel region to said drain region and so that said field effect transistor has a specific drain-to-body breakdown voltage.