BODY-BIASED SWITCHING DEVICE

• US 20140227983A1
• Filed: 02/11/2013
• Published: 08/14/2014
• Est. Priority Date: 02/11/2013
• Status: Active Grant

• Current Assignee: Qorvo US, Inc. (Qorvo, Inc.)
• Original Assignee: TriQuint Semiconductor Incorporated (Qorvo, Inc.)
• Inventors: Furino, James P. Jr., Clausen, William J., Yore, Michael D.
• Granted Patent: US 9,214,932 B2
• Time in Patent Office: Days
• US Class Current: 455/78
• CPC Class Codes: H01L 29/78 with field effect produced by an insulated gate H01L29/7725, H01L29/775, H01L29/778 take precedence
• CPC Class Codes: H03K 17/063 in field-effect transistor switches
• CPC Class Codes: H03K 17/162 without feedback from the output circuit to the control circuit
• CPC Class Codes: H03K 2017/066 Maximizing the OFF-resistance instead of minimizing the ON-resistance
• CPC Class Codes: H03K 2217/0018 Special modifications or use of the back gate voltage of a FET

Abstract

Embodiments provide a switching device including one or more field-effect transistors (FETs). In embodiments, a body-bias circuit may derive a bias voltage based on a radio frequency signal applied to a switch field-effect transistor and apply the bias voltage to the body terminal of the switch field-effect transistor.

Claims

1. A circuit configured to switch radio-frequency (“

RF”

) signals, the circuit comprising;

a field-effect transistor (“

FET”

) including a source terminal, a gate terminal, a drain terminal, and a body terminal; and

a body-bias circuit coupled with the source terminal, the drain terminal and the body terminal, the body-bias circuit configured to;

derive a negative bias voltage based on an RF signal applied to the FET; and

provide the negative bias voltage to the body terminal when the FET is in an off state.

2. The circuit of claim 1, further comprising:

a plurality of FETs, including the FET, coupled in series with one another.

3. The circuit of claim 1, wherein the FET is an n-type FET.

4. The circuit of claim 1, wherein the body-bias circuit is only coupled with the source terminal, the drain terminal, and the body terminal.

5. The circuit of claim 1, wherein the circuit comprises a silicon-on-insulator (“

SOI”

) circuit.

6. The circuit of claim 1, wherein the FET is a first FET and the body-bias circuit comprises:

a node coupled with the body terminal;

a second FET having;

a source terminal coupled with the source terminal of the first FET; and

a drain terminal coupled with the node; and

a third FET having;

a drain terminal coupled with the node; and

a source terminal coupled with the drain terminal of the first FET.

7. The circuit of claim 6, wherein:

the second FET further includes a gate terminal coupled with the drain terminal of the first FET; and

the third FET further includes a gate terminal coupled with the source terminal of the first FET.

8. The circuit of claim 6, wherein the first and second FETs are diode-connected FETs and:

the second FET further includes a gate terminal coupled with the node; and

the third FET further includes a gate terminal coupled with the node.

9. The circuit of claim 1, wherein the body-bias circuit comprises:

a node coupled with the body terminal;

a first diode coupled with the source terminal and the node; and

a second diode coupled with the drain terminal and the node.

10. The circuit of claim 1, wherein:

the first diode includes a cathode terminal coupled with the source terminal and an anode terminal coupled with the node; and

the second diode includes a cathode terminal coupled with the drain terminal and an anode terminal coupled with the node.

11. The circuit of claim 1, wherein the body-bias circuit is to derive the negative bias voltage by being configured to rectify the RF signal.

12. A wireless communication device comprising:

a transceiver;

an antenna; and

a radio frequency (“

RF”

) front-end coupled with the transceiver and the antenna and configured to communicate signals between the transceiver and the antenna, the radio frequency front-end including a silicon-on-insulator switching device that has;

a decoder configured to set a plurality of switch field-effect transistors (“

FET”

) in an off state or an on state; and

a cell with a field-effect transistor (“

FET”

) of the plurality of FETs and a body-bias circuit, wherein the body-bias circuit is configured to provide a negative voltage to a body of the field-effect transistor when the FET is in an off-state, the negative voltage derived from an RF signal applied to the FET.

13. The wireless communication device of claim 12, wherein the FET is a first FET and the body-bias circuit comprises:

a node coupled with a body terminal of the first FET;

a second FET having;

a source terminal coupled with a source terminal of the first FET; and

a drain terminal coupled with the node; and

a third FET having;

a drain terminal coupled with the node; and

a source terminal coupled with the drain terminal of the first FET.

14. The wireless communication device of claim 13, wherein:

the second FET further includes a gate terminal coupled with the drain terminal of the first FET; and

the third FET further includes a gate terminal coupled with the source terminal of the first FET.

15. A method comprising:

controlling, with a decoder circuit, a switch field-effect transistor (“

FET”

) to be in an off state;

deriving, with a body-bias circuit, a negative bias voltage based on a radio-frequency (“

RF”

) signal applied to the switch FET while the switch FET is in the off state; and

providing, by the body-bias circuit, the negative bias voltage to a body of the switch FET while the switch FET is in the off state.

16. The method of claim 15, wherein deriving the negative bias voltage comprises:

rectifying the RF signal applied to the switch FET.

17. A circuit configured to switch radio-frequency (“

RF”

) signals, the circuit comprising;

a field-effect transistor (“

FET”

) including a source terminal, a gate terminal, a drain terminal, and a body terminal; and

a body-bias circuit having;

a node coupled with the body terminal;

a first resistor coupled with the drain terminal and the node; and

a second resistor coupled with the source terminal and the node,

wherein the body-bias circuit is configured to;

derive a bias voltage based on an RF signal applied to the FET; and

provide the bias voltage to the body terminal.

18. The circuit of claim 17, wherein the first resistor and the second resistor are of equal size.

19. The circuit of claim 17, wherein the body-bias circuit is configured to provide the bias voltage as a DC voltage of approximately zero volts.

20. The circuit of claim 17, wherein the gate terminal of the FET is coupled with a decoder;

and the drain terminal of the FET is not coupled with the decoder.