CONTROLLING POWER MANAGEMENT IN MICRO-SERVERS

• US 20140237278A1
• Filed: 03/31/2012
• Published: 08/21/2014
• Est. Priority Date: 03/31/2012
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Kumar, Anil K.
• Granted Patent: US 9,454,210 B2
• Time in Patent Office: Days
• US Class Current: 713/323
• CPC Class Codes: G06F 1/3206 Monitoring of events, devices or parameters that trigger a change in power modality
• CPC Class Codes: G06F 1/3215 Monitoring of peripheral devices
• CPC Class Codes: G06F 1/3234 Power saving characterised by the action undertaken
• CPC Class Codes: G06F 1/325 Power saving in peripheral device

Abstract

Systems and methods of enabling power management in a micro server include providing multiple cores, a power management module coupled to the cores, and one or more peripherals coupled to the power management module. The power management module may be configured to cause the one or more peripherals to delay operations based on determining that the cores are in a first power consumption state, and place the cores in a second power consumption state for a predetermined time period. The second power consumption state may consume less power than the first power consumption state. The power management module may cause the one or more peripherals to resume their operations based on expiration of the predetermined time period and may place the cores in a third power consumption state based on the expiration of the time period.

Claims

1-25. -25. (canceled)

26. An apparatus comprising:

logic to transmit a first notification to one or more peripherals using side band messages to cause the one or more peripherals to delay operations, wherein the first notification is transmitted based on cores of a micro server being placed into a first power consumption state;

logic to place the cores into a second power consumption state that is to consume less power than the first power consumption state;

logic to start a timer for a time period, wherein the cores are configured to stay in the second power consumption state for the time period; and

logic to transmit a second notification to the one or more peripherals using the side band messages that the cores of the micro server are being placed into a third power consumption state upon expiration of the time period, wherein the third power consumption state is to consume more power than the first and second power consumption states.

27. The apparatus of claim 26, wherein at least one of the one or more peripherals is to be configured to align interrupts or to buffer data during the time period.

28. The apparatus of claim 27, wherein the one or more peripherals are to be configured to stop buffering the data or aligning the interrupts upon receiving the second notification.

29. The apparatus of claim 26, further comprising:

logic to enable taking the cores out of the second power consumption state upon receiving an indication that the one or more peripherals are unable to continue buffering the data or aligning the interrupts without data loss.

30. The apparatus of claim 26, wherein the first and second notifications are to be transmitted to a Gigabit Ethernet (GbE) controller.

31. The apparatus of claim 26, wherein the first and second notifications are to be transmitted to a Serial Advanced Technology Attachment (SATA) controller.

32. The apparatus of claim 26, wherein the time period is programmable, wherein the second power consumption state is a sleep state, and wherein the cores are associated with a socket.

33. The apparatus of any of the claim 32, wherein the socket includes the cores and other socket components, and wherein power consumption of one or more of the other socket components of the socket is reduced based on the cores being placed in the second power consumption state.

34. A computer-implemented method comprising:

using side band communication, causing one or more peripherals of a server having multiple cores to delay operations based on determining that the cores are being placed into a first power consumption state;

placing the cores into a second power consumption state for a time period, the second power consumption state consuming less power than the first power consumption state;

using the side band communication, causing the one or more peripherals to resume operations based on an expiration of the time period; and

placing the cores into a third power consumption state based on the expiration of the time period, the third power consumption state consuming more power than the first power consumption state and the second power consumption state.

35. The method of claim 34, further comprising:

placing the cores into the third power consumption state based on receiving an indication that the one or more peripherals are unable to continue to delay their operations before the expiration of the time period.

36. The method of claim 35, wherein the cores are associated with a first socket of a micro server module having the first socket and a second socket.

37. The method of claim 36, wherein power consumption of cores associated with the second socket is configured independently of power consumption of the cores associated with the first socket.

38. The method of claim 35, wherein the sideband communications are conducted with a Gigabit Ethernet controller.

39. The method of claim 38, wherein the Gigabit Ethernet controller is to delay operations by aligning interrupts.

40. The method of claim 35, wherein the sideband communications are conducted with a Serial Advanced Technology Attachment (SATA) controller.

41. The method of claim 40, wherein the SATA controller is to delay operations by buffering data.

42. A system comprising:

multiple cores;

a power management module coupled to the cores; and

one or more peripherals coupled to the power management module, wherein the power management module is configured to;

cause the one or more peripherals to delay operations based on determining that the cores are in a first power consumption state;

place the cores in a second power consumption state for a time period, the second power consumption state consuming less power than the first power consumption state;

cause the one or more peripherals to resume their operations based on expiration of the time period; and

place the cores in a third power consumption state based on the expiration of the time period, the third power consumption state consuming more power than the first power consumption state and the second power consumption state.

43. The system of claim 42, wherein the power management module is configured to communicate with the one or more peripherals using side band communications.

44. The system of claim 43, wherein the power management module is configured to place the cores in the third power consumption state based on receiving an indication that the one or more peripherals not being able to continue delaying their operations.

45. The system of claim 44, wherein the one or more peripherals include a Gigabit Ethernet controller, and wherein the Gigabit Ethernet controller is to delay operations by aligning interrupts.

46. The system of claim 44, wherein the one or more peripherals include a Serial Advanced Technology Attachment (SATA) controller, and wherein the SATA controller is to delay operations by buffering data.

47. The system of claim 44, wherein the cores are associated with a first socket of a micro server module having the first socket and a second socket.

48. The system of claim 47, wherein power consumption of cores associated with the second socket is configured independently of power consumption of the cores associated with the first socket.

49. The system of claim 48, wherein the first socket includes the cores and other socket components, and wherein power consumption of one or more of the other socket components of the first socket is to be reduced based on the cores being placed in the second power consumption state.

50. The system of claim 42, wherein the time period is to be programmable.