SEMICONDUCTOR PACKAGE INCLUDING ANTENNA SUBSTRATE AND MANUFACTURING METHOD THEREOF

• US 20140247195A1
• Filed: 03/04/2013
• Published: 09/04/2014
• Est. Priority Date: 03/04/2013
• Status: Active Grant

• Current Assignee: Advanced Semiconductor Engineering Inc (ASE Technology Holding Co., Ltd.)
• Original Assignee: Advanced Semiconductor Engineering Inc (ASE Technology Holding Co., Ltd.)
• Inventors: Yen, Han-Chee
• Granted Patent: US 9,837,701 B2
• Time in Patent Office: Days
• US Class Current: 343/873
• CPC Class Codes: H01L 21/561 Batch processing
• CPC Class Codes: H01L 2223/6677 for antenna, e.g. antenna included within housing of semiconductor device antennas per se H01Q
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/04042 Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
• CPC Class Codes: H01L 2224/04073 Bonding areas specifically adapted for connectors of different types
• CPC Class Codes: H01L 2224/13025 the bump connector being disposed on a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/16145 the bodies being stacked
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/73207 Bump and wire connectors
• CPC Class Codes: H01L 2224/73253 Bump and layer connectors
• CPC Class Codes: H01L 2224/73257 Bump and wire connectors
• CPC Class Codes: H01L 2224/81 using a bump connector
• CPC Class Codes: H01L 2224/85 using a wire connector
• CPC Class Codes: H01L 2224/97 the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 23/3128 the substrate having spherical bumps for external connection
• CPC Class Codes: H01L 23/66 High-frequency adaptations
• CPC Class Codes: H01L 24/97 the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 25/16 the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/12042 : LASER
• CPC Class Codes: H01L 2924/15192 : Resurf arrangement of the internal vias
• CPC Class Codes: H01L 2924/15313 : being a land array, e.g. LGA
• CPC Class Codes: H01L 2924/15787 : Ceramics, e.g. crystalline carbides, nitrides or oxides
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/19105 : in a side-by-side arrangement on a common die mounting substrate
• CPC Class Codes: H01L 2924/19107 : off-chip wires
• CPC Class Codes: H01L 2924/3025 : Electromagnetic shielding
• CPC Class Codes: H01Q 1/2283 : mounted in or on the surface of a semiconductor substrate as a chip-type antenna or integrated with other components into an IC package
• CPC Class Codes: H01Q 9/0407 : Substantially flat resonant element parallel to ground plane, e.g. patch antenna dipole H01Q9/285; monopole H01Q9/40

Abstract

A semiconductor package includes a package substrate, a semiconductor device, an antenna substrate and a package body. The semiconductor device is disposed on an upper surface of the package substrate. The antenna substrate is disposed on the semiconductor device and includes a core layer, a grounding layer formed on a lower surface of the core layer, and an antenna layer formed on an upper surface of the core layer and electrically connected to the grounding layer through a conductive via of the core layer. The package body encapsulates the semiconductor device and the antenna substrate.

Claims

1. A semiconductor package comprising:

a package substrate including an upper surface;

a semiconductor device disposed adjacent to the upper surface of the package substrate;

an antenna substrate disposed on the semiconductor device, the antenna substrate including;

a core layer including an upper surface, a lower surface and a conductive via;

a grounding layer formed on the lower surface of the core layer; and

an antenna layer formed on the upper surface of the core layer and electrically connected to the grounding layer through the conductive via; and

a package body encapsulating the semiconductor device and the antenna substrate.

2. The semiconductor package of claim 1, wherein the grounding layer includes a feeding portion and a grounding portion, and the grounding portion is spaced from and surrounds the feeding portion.

3. The semiconductor package of claim 1, wherein the grounding layer covers the entire lower surface of the core layer.

4. The semiconductor package of claim 1, wherein the semiconductor device includes

a chip including an upper surface and a feeding conductive via;

and

a feeding layer formed on the upper surface of the chip;

wherein the antenna substrate is electrically connected to the package substrate through the feeding layer and the feeding conductive via.

5. The semiconductor package of claim 1,

wherein the semiconductor device includes a chip with an upper surface and a grounding conductive via, and further includes a grounding layer formed on the upper surface of the chip, and

wherein the antenna substrate is electrically connected to the package substrate through the grounding layer and the grounding conductive via.

6. The semiconductor package of claim 1, wherein the antenna layer of the antenna substrate is exposed from the package body.

7. The semiconductor package of claim 1, wherein the antenna layer of the antenna substrate includes a grounding portion and an antenna portion, and the semiconductor package further comprises:

a feeding wire connecting the antenna portion and the package substrate; and

a grounding wire connecting the grounding portion and the package substrate.

8. The semiconductor package of claim 1, further comprising:

a passive component disposed on the package substrate;

wherein the antenna substrate at least partially extends over the passive component.

9. A semiconductor package comprising:

a package substrate including an upper surface;

a chip disposed adjacent to the upper surface of the package substrate;

a wire electrically connecting the chip and the package substrate;

a spacer substrate disposed on the chip;

an antenna substrate disposed on the spacer substrate and comprising;

a core layer including an upper surface, a lower surface, and a conductive via;

a grounding layer formed on the lower surface of the core layer; and

an antenna layer formed on the upper surface of the core layer and electrically connected to the grounding layer through the conductive via; and

a package body encapsulating the chip, the spacer substrate and the antenna substrate.

10. The semiconductor package of claim 9, wherein the grounding layer includes a feeding portion and a grounding portion, and the grounding portion is spaced from and surrounds the feeding portion.

11. The semiconductor package of claim 9, wherein the grounding layer covers the entire lower surface of the core layer.

12. The semiconductor package of claim 9, wherein the spacer substrate is an interposer substrate disposed between the chip and the antenna substrate and includes a conductive via electrically connected to the antenna substrate and the chip.

13. The semiconductor package of claim 12, wherein the interposer substrate includes an upper surface, a feeding layer formed at the upper surface of the interposer substrate and a feeding conductive via, and the antenna substrate is electrically connected to the chip through the feeding layer and the feeding conductive via.

14. The semiconductor package of claim 12, wherein the interposer substrate includes an upper surface, a grounding layer formed at the upper surface of the interposer substrate and a grounding conductive via, and the antenna substrate is electrically connected to the chip through the grounding layer of the interposer substrate and the grounding conductive via.

15. The semiconductor package of claim 9, wherein the chip includes an active surface facing the spacer substrate.

16. The semiconductor package of claim 9, wherein the antenna layer is exposed from the package body.

17. The semiconductor package of claim 9, wherein the antenna layer of the antenna substrate includes a feeding portion and a grounding portion, and the semiconductor package includes:

a feeding wire connecting the feeding portion of the antenna layer and the package substrate; and

a grounding wire connecting the grounding portion of the antenna layer and the package substrate.

18. The semiconductor package of claim 9, further comprising:

a passive component disposed on the package substrate;

wherein the antenna substrate at least partially extends over the passive component.

19. A method of making a semiconductor package, comprising:

providing a package substrate, wherein the package substrate includes an upper surface;

disposing a chip on the upper surface of the package substrate;

providing an antenna substrate,

wherein the antenna substrate is verified to be a working antenna substrate; and

wherein the antenna substrate includes

a core layer including an upper surface, a lower surface and a conductive via;

a grounding layer formed on the lower surface of the core layer; and

an antenna layer formed on the upper surface of the core layer and electrically connected to the grounding layer through the conductive via;

disposing the antenna substrate on the chip; and

forming a package body encapsulating the chip, a portion of the upper surface of the substrate and the antenna substrate.

20. The method of claim 19, further comprising disposing a spacer substrate on the chip prior to disposing the antenna substrate on the chip.