CHIP PACKAGE AND METHOD FOR FORMING THE SAME
First Claim
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1. A chip package, comprising:
- a semiconductor substrate;
a device region formed in the semiconductor substrate;
at least one conducting pad disposed over a surface of the semiconductor substrate;
a protection substrate disposed over the surface of the semiconductor substrate; and
a spacer layer disposed between the surface of the semiconductor substrate and the protection substrate, wherein the protection substrate and the spacer layer surround a cavity over the device region, the spacer layer has an outer side surface away from the cavity, and the outer side surface of the spacer layer is not a cutting surface.
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Abstract
An embodiment of the invention provides a chip package which includes: a semiconductor substrate; a device region formed in the semiconductor substrate; at least a conducting pad disposed over a surface of the semiconductor substrate; a protection plate disposed over the surface of the semiconductor substrate; and a spacer layer disposed between the surface of the semiconductor substrate and the protection plate, wherein the protection plate and the spacer layer surround a cavity over the device region, the spacer layer has an outer side surface away from the cavity, and the outer side surface of the spacer layer is not a cutting surface.
21 Citations
21 Claims
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1. A chip package, comprising:
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a semiconductor substrate; a device region formed in the semiconductor substrate; at least one conducting pad disposed over a surface of the semiconductor substrate; a protection substrate disposed over the surface of the semiconductor substrate; and a spacer layer disposed between the surface of the semiconductor substrate and the protection substrate, wherein the protection substrate and the spacer layer surround a cavity over the device region, the spacer layer has an outer side surface away from the cavity, and the outer side surface of the spacer layer is not a cutting surface. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11. A method for forming a chip package, comprising:
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providing a semiconductor substrate, wherein at least one device region is formed in the semiconductor substrate, and at least one conducting pad is disposed over a surface of the semiconductor substrate; providing a protection substrate; disposing a spacer layer over the surface of the semiconductor substrate or over the protection substrate; disposing a sacrificial support layer over the surface of the semiconductor substrate or over the protection substrate; disposing the protection substrate over the surface of the semiconductor substrate such that the protection substrate and the spacer layer surround a cavity over the at least one device region; and dicing and removing a portion of the protection substrate and a portion of the sacrificial support layer to expose the at least one conducting pad. - View Dependent Claims (12, 13, 14, 15, 16, 17, 18, 19, 20, 21)
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Specification