Nonvolatile Charge Trap Memory Device Having a Deuterated Layer in a Multi-Layer Charge-Trapping Region

• US 20140264550A1
• Filed: 03/25/2014
• Published: 09/18/2014
• Est. Priority Date: 05/25/2007
• Status: Active Grant

• Current Assignee: Longitude Flash Memory Solutions, Ltd. (Vector Capital Corporation)
• Original Assignee: Cypress Semiconductor Corporation (Infineon Technologies AG)
• Inventors: Levy, Sagy Charel, Jenne, Frederick B., Ramkumar, Krishnaswamy
• Granted Patent: US 10,079,314 B2
• Time in Patent Office: Days
• US Class Current: 257/324
• CPC Class Codes: H01L 29/40117 the electrodes comprising a charge-trapping insulator
• CPC Class Codes: H01L 29/513 the variation being perpendicular to the channel plane
• CPC Class Codes: H01L 29/66833 with a charge trapping gate insulator, e.g. MNOS transistors
• CPC Class Codes: H01L 29/792 with charge trapping gate insulator, e.g. MNOS-memory transistors

Abstract

A nonvolatile charge trap memory device is described. The device includes a substrate having a channel region. A gate stack is disposed above the substrate over the channel region. The gate stack includes a multi-layer charge-trapping region having a first deuterated layer. The multi-layer charge-trapping region may further include a deuterium-free charge-trapping layer.

Claims

1-20. -20. (canceled)

21. A nonvolatile charge trap memory device, comprising:

a gate stack disposed above a channel region of a substrate, wherein the gate stack comprises a multi-layer charge-trapping region comprising a first layer and a second layer, the first layer disposed between the channel region and the second layer, wherein the first layer comprises a first deuterium gradient that decreases from a first deuterium concentration near the channel region to a second deuterium concentration near the second layer.

22. The nonvolatile charge trap memory device of claim 21, wherein the multi-layer charge-trapping region further comprises a third layer, the second layer disposed is between the first layer and the third layer, wherein the third layer comprises a second deuterium gradient that increases from a third deuterium concentration near the second layer to a fourth deuterium concentration near a top surface of the third layer.

23. The nonvolatile charge trap memory device of claim 21, wherein the second layer is a charge trapping layer.

24. The nonvolatile charge trap memory device of claim 21, further comprising:

a dielectric layer disposed above the multi-layer charge-trapping region.

25. The nonvolatile charge trap memory device of claim 24, wherein the dielectric layer is a high-k dielectric layer comprising at least one of hafnium oxide, zirconium oxide, hafnium silicate, hafnium oxy-nitride, hafnium zirconium oxide, or lanthanum oxide.

26. The nonvolatile charge trap memory device of claim 24, wherein the dielectric layer comprises deuterium.

27. The nonvolatile charge trap memory device of claim 24, wherein a thickness of the dielectric layer is in a range of 1-20 nanometers.

28. The nonvolatile charge trap memory device of claim 24, further comprising:

a metallic gate layer disposed above the dielectric layer.

29. The nonvolatile charge trap memory device of claim 21, wherein the gate stack is further disposed between a source region and a drain region.

30. A nonvolatile charge trap memory device, comprising:

a gate stack disposed over a channel region of a substrate, wherein the gate stack comprises a multi-layer charge-trapping region having a first deuterated trap-free layer and a second deuterium-free trapping layer, wherein the charge-trapping region comprises a first abrupt interface between the first deuterated trap-free layer and the second deuterium-free trapping layer.

31. The nonvolatile charge trap memory device of claim 30, wherein the first abrupt interface is defined by a junction that separates a finite deuterium concentration of the first deuterated trap-free layer from a zero deuterium concentration of the second deuterium-free trapping layer.

32. The nonvolatile charge trap memory device of claim 30, wherein the multi-layer charge-trapping region further comprises a third deuterated trap-free layer, wherein the second deuterium-free trapping layer is between the first and third deuterated trap-free layers, wherein the charge-trapping region comprises a second abrupt interface between the third deuterated trap-free layer and the second deuterium-free trapping layer.

33. The nonvolatile charge trap memory device of claim 30, further comprising:

a dielectric layer disposed above the multi-layer charge-trapping region.

34. The nonvolatile charge trap memory device of claim 32, wherein the dielectric layer is a high-k dielectric layer comprising at least one of hafnium oxide, zirconium oxide, hafnium silicate, hafnium oxy-nitride, hafnium zirconium oxide, or lanthanum oxide.

35. The nonvolatile charge trap memory device of claim 32, wherein the dielectric layer comprises deuterium.

36. The nonvolatile charge trap memory device of claim 32, further comprising:

a metallic gate layer disposed above the dielectric layer.

37. The nonvolatile charge trap memory device of claim 30, wherein the gate stack is further disposed between a source region and a drain region.

38. A method comprising:

forming a tunnel dielectric layer on a top surface of a substrate; and

forming a multi-layer charge trapping region on the top surface of the tunnel dielectric layer, wherein the multi-layer charge trapping region comprises a first layer and a second layer, the first layer disposed between the tunnel dielectric layer and the second layer, wherein the first layer comprises a first deuterium gradient that decreases from a first deuterium concentration near the tunnel dielectric layer to a second deuterium concentration near the second layer.

39. The method of claim 38, wherein the multi-layer charge-trapping region further comprises a third layer, wherein the second layer is between the first layer and the third layer, and wherein the third layer comprises a second deuterium gradient that increases from a third deuterium concentration near the second layer to a fourth deuterium concentration near a top surface of the third layer.

40. The method of claim 39, further comprising:

forming a high-k dielectric layer disposed on the top surface of the third layer, the high-k dielectric layer comprising at least one of hafnium oxide, zirconium oxide, hafnium silicate, hafnium oxy-nitride, hafnium zirconium oxide, or lanthanum oxide.