Tiered Access to On Chip Features

• US 20140283119A1
• Filed: 03/13/2013
• Published: 09/18/2014
• Est. Priority Date: 03/13/2013
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Sandri, Jason G., Ahmed, Monib, Walker, Ian S.
• Granted Patent: US 9,292,713 B2
• Time in Patent Office: Days
• US Class Current: 726/28
• CPC Class Codes: G06F 21/10 Protecting distributed programs or content, e.g. vending or licensing of copyrighted material protection in video systems or pay television H04N7/16 ; Digital rights management [DRM]
• CPC Class Codes: G06F 21/76 in application-specific integrated circuits [ASIC] or field-programmable devices, e.g. field-programmable gate arrays [FPGA] or programmable logic devices [PLD]
• CPC Class Codes: G06F 21/85 interconnection devices, e.g. bus-connected or in-line devices
• CPC Class Codes: G06F 2221/034 Test or assess a computer or a system
• CPC Class Codes: H04L 9/32 including means for verifying the identity or authority of a user of the system or for message authentication, e.g. authorization, entity authentication, data integrity or data verification, non-repudiation, key authentication or verification of credentials

Abstract

In accordance with some embodiments, multiple blind debug passwords are provided. Each of a plurality of interested entities may have its own password and each password may unlock a specific set of features offered by an integrated circuit. In some embodiments each entity does not know the other passwords of the other entities. Potentially interested entities include an integrated circuit end customer, the original equipment manufacturer, the entity that provided the features to the integrated circuit and a conditional access provider. All debug features may be controlled solely via access to the debug tiers which are accessed by multiple debug passwords. Lower tier passwords are required in order to access higher tiers. Debug features may be separated into multiple tiers with more intrusive access requiring multiple debug passwords in order to gain access.

Claims

1. An apparatus comprising:

a fuse array; and

a controller to limit access to said fuse array, said controller to provide at least two tiers of access, to different information, each tier requiring a different password.

2. The apparatus of claim 1 wherein said controller to require a first password to access each of said tiers and a second password to access only one of said tiers.

3. The apparatus of claim 1 including at least three tiers, each involving different passwords.

4. The apparatus of claim 1, said controller to enable use of a master password to access both tiers.

5. The apparatus of claim 1 wherein said apparatus limits access to debug information.

6. The apparatus of claim 3 wherein each password allows access to a particular feature set.

7. The apparatus of claim 3 wherein each higher tier requires the same passwords used to access lower tiers and an additional password.

8. The apparatus of claim 1 including a public password-free tier.

9. The apparatus of claim 1 including an operating system.

10. The apparatus of claim 1 including a battery.

11. The apparatus of claim 1 including firmware and a module to update said firmware.

12. A method comprising:

providing at least two tiers of access to a fuse array, each tier storing different information; and

requiring a different password for each tier.

13. The method of claim 12 including requiring a first password to access each of said tiers and a second password to access only one of said tiers.

14. The method of claim 12 including using at least three tiers and requiring a different password for each tier.

15. The method of claim 12 including enabling use of a master password to access both tiers.

16. The method of claim 12 including limiting access to debug information.

17. The method of claim 14 including allowing access via each password to a particular feature set.

18. The method of claim 14 including requiring one password that is the same for each of said three tiers and, in addition, requiring an additional password for at least one of said higher tiers.

19. The method of claim 14 including providing a public password free tier.

20. One or more non-transitory computer readable media storing instructions executed by a processor to perform a sequence comprising:

providing at least two tiers of access to a fuse array, each tier storing different information; and

requiring a different password for each tier.

21. The computer readable media of claim 20, said sequence including requiring a first password to access each of said tiers and a second password to access only one of said tiers.

22. The computer readable media of claim 20, said sequence including using at least three tiers and requiring a different password for each tier.

23. The computer readable media of claim 20, said sequence including enabling use of a master password to access both tiers.

24. The computer readable media of claim 20, said sequence including limiting access to debug information.

25. The computer readable media of claim 22, said sequence including allowing access via each password to a particular feature set.

26. The computer readable media of claim 22, said sequence including requiring one password that is the same for each of said three tiers and, in addition, requiring an additional password for at least one of said higher tiers.

27. The computer readable media of claim 22, said sequence including providing a public password free tier.