MINIMIZING PLATING STUB REFLECTIONS IN A CHIP PACKAGE USING CAPACITANCE

• US 20140284217A1
• Filed: 06/03/2014
• Published: 09/25/2014
• Est. Priority Date: 09/25/2008
• Status: Abandoned Application

• Current Assignee: AquaSmart Enterprises, LLC, Lenovo Enterprise Solutions (Singapore) Pte., Ltd. (Lenovo Group Ltd.)
• Original Assignee: International Business Machines Corporation
• Inventors: Mutnury, Bhyrav M., Cases, Moises, Na, Nanju, Kim, Tae Hong
• Application Number:
  US14/294,837
• Publication Number:
  US 20140284217A1
• Time in Patent Office: Days
• US Class Current: 205/125
• CPC Class Codes: C25D 5/02 Electroplating of selected surface areas
• CPC Class Codes: H01L 21/4853 Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 24/73 Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/14 Integrated circuits
• CPC Class Codes: H01L 2924/15311 being a ball array, e.g. BGA
• CPC Class Codes: H05K 1/0231 Capacitors or dielectric substances
• CPC Class Codes: H05K 1/162 incorporating printed capacitors
• CPC Class Codes: H05K 2203/049 Wire bonding
• CPC Class Codes: H05K 3/242 characterised by using temporary conductors on the printed circuit for electrically connecting areas which are to be electroplated

Abstract

The present invention is directed to shifting the resonant frequency in a high-frequency chip package away from an operational frequency by connecting a capacitance between an open-ended plating stub and ground. One embodiment provides a method including capacitively coupling a plating stub to ground so that the resonant frequency caused by the plating stub in a semiconductor package is shifted away from an operational frequency.

Claims

1. A method, comprising:

capacitively coupling a plating stub to ground so that the resonant frequency caused by the plating stub in a semiconductor package is shifted away from an operational frequency.

2. The method of claim 1, further comprising:

forming the plating stub by electroplating a portion of a substrate along an electrical pathway extending from a periphery of the substrate to the portion of the substrate being electroplated.

3. The method of claim 1, wherein capacitively coupling the plating stub to ground includes connecting a first lead of a capacitor to the plating stub and a second lead of the capacitor to ground.

4. The method of claim 1, wherein capacitively coupling the plating stub to ground includes forming an embedded capacitor in the substrate that couples the plating stub in an outer layer to a ground layer spaced from the outer layer.

5. The method of claim 1, wherein the semiconductor package includes a ground layer and a first outer layer, wherein the first outer layer provides a chip mounting location, a signal interconnect spaced from the chip mounting location, a signal trace extending from near the chip mounting location to the signal interconnect, and the plating stub, wherein the plating stub extends from the signal interconnect.