SEMICONDUCTOR APPARATUS

• US 20140284711A1
• Filed: 09/10/2013
• Published: 09/25/2014
• Est. Priority Date: 03/22/2013
• Status: Active Grant

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Kawaguchi, Yusuke, Katoh, Shunsuke
• Granted Patent: US 9,224,823 B2
• Time in Patent Office: Days
• US Class Current: 257/331
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/41741 for vertical or pseudo-vertical devices
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/4238 characterised by the surface lay-out
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/7828 without inversion channel, e.g. vertical ACCUFETs, normally-on vertical MISFETs

Abstract

A semiconductor apparatus includes a drain region of a first-conductivity type, a drain electrode electrically coupled to the drain region, and a semiconductor layer of the first-conductivity type formed onto the drain region and having a first impurity concentration. The semiconductor apparatus further includes: a source region of the first-conductivity type formed on the semiconductor layer and having a second impurity concentration; a first source electrode electrically coupled to the source region; and a gate electrode formed via an insulating layer. The one end of the gate electrode is in a depth of the source region, and the other end is in a depth of the semiconductor layer or the drain region. A second source electrode is provided in the semiconductor layer under the gate electrodes via an insulating layer. A second spacing between the second source electrodes is larger than a first spacing between the gate electrodes.

Claims

1. A semiconductor apparatus comprising:

a drain region of a first conductivity type;

a drain electrode electrically coupled to the drain region;

a semiconductor layer of the first conductivity type formed onto the drain region, the semiconductor layer having a first impurity concentration;

a source region of the first conductivity type formed on the semiconductor layer, the source region having a second impurity concentration greater than the first impurity concentration;

a first source electrode electrically coupled to the source region;

a gate electrode formed via an insulating layer, the gate electrode having one end and another end, the one end being in a depth of the source region, and the other end being in a depth of the semiconductor layer or the drain region; and

a second source electrode provided in the semiconductor layer under the gate electrodes via an insulating layer, the second source electrode being electrically coupled to the first source electrode, wherein

a second spacing in between a plurality of the second source electrodes is configured larger than a first spacing in between a plurality of the gate electrodes.

2. The semiconductor apparatus according to claim 1, wherein

an upper layer portion of the semiconductor layer has a third impurity concentration smaller than the first impurity concentration.

3. The semiconductor apparatus according to claim 1, wherein

the second source electrode is embedded in a position under a part of the plurality of the gate electrodes.

4. The semiconductor apparatus according to claim 3, wherein

the second source electrode has a smaller width in a first direction than the gate electrodes.

5. The semiconductor apparatus according to claim 3, wherein

the second source electrode has a same width in a first direction as a width of the gate electrodes in the first direction.

6. The semiconductor apparatus according to claim 3, wherein

an upper layer portion of the semiconductor layer has a third impurity concentration smaller than the first impurity concentration.

7. The semiconductor apparatus according to claim 1, further comprising:

a first trench extending downward from a surface of the semiconductor layer to have a first depth, the first trench interiorly including the gate electrode and including the second source electrode under the gate electrode; and

a second trench extending downward from a surface of the semiconductor layer to have a second depth smaller than the first depth, the second trench interiorly including the gate electrode alone.

8. The semiconductor apparatus according to claim 7, wherein

an upper layer portion of the semiconductor layer has a third impurity concentration smaller than the first impurity concentration.

9. The semiconductor apparatus according to claim 7, wherein

the second source electrode has a width in a first direction smaller than the gate electrode.

10. The semiconductor apparatus according to claim 7, wherein

the second source electrode has a same width in a first direction as a width of the gate electrode in the first direction.

11. The semiconductor apparatus according to claim 1, further comprising:

an upper trench extending downward from a surface of the semiconductor layer, the upper trench having a first width, the upper trench interiorly including the gate electrode; and

a lower trench extending downward from a bottom end of the upper trench, the lower trench having a second width smaller than the first width, the lower trench interiorly including the second source electrode.

12. The semiconductor apparatus according to claim 11, wherein

an upper layer portion of the semiconductor layer has a third impurity concentration smaller than the first impurity concentration.

13. The semiconductor apparatus according to claim 11, wherein

the second source electrode has a width in a first direction smaller than the gate electrode.

14. A semiconductor apparatus comprising:

a drain region of a first conductivity type;

a drain electrode electrically coupled to the drain region;

a semiconductor layer of the first conductivity type formed onto the drain region, the semiconductor layer having a first impurity concentration;

a source region of the first conductivity type formed on the semiconductor layer, the source region having a second impurity concentration greater than the first impurity concentration;

a first source electrode electrically coupled to the source region;

a plurality of gate electrodes formed in the semiconductor layer via an insulating layer, the plurality of gate electrodes having a first depth from a surface of the semiconductor layer; and

a second source electrode formed in the semiconductor layer via an insulating film so as to be interposed between the gate electrodes, the second source electrode having a second depth from the surface of the semiconductor layer greater than the first depth, and the second source electrode being electrically coupled to the first source electrode.

15. The semiconductor apparatus according to claim 14, wherein

the gate electrodes are configured in a form of mesh extending in a direction in parallel with the drain region;

and

the second source electrode is formed in a mesh area partitioned by the gate electrodes.

16. The semiconductor apparatus according to claim 14, wherein

an upper layer portion of the semiconductor layer has a third impurity concentration smaller than the first impurity concentration.