MEMORY DEVICES HAVING SOURCE LINES DIRECTLY COUPLED TO BODY REGIONS AND METHODS
First Claim
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1. A method for erasing a memory cell string, comprising:
- biasing a plurality of gates to a first voltage;
biasing a source line to a second voltage, wherein the source line is directly coupled to an elongated body region of the string, the second voltage being different than the first voltage.
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Abstract
Memory devices, memory cell strings and methods of operating memory devices are shown. Configurations described include directly coupling an elongated body region to a source line. Configurations and methods shown should provide a reliable bias to a body region for memory operations such as erasing.
17 Citations
20 Claims
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1. A method for erasing a memory cell string, comprising:
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biasing a plurality of gates to a first voltage; biasing a source line to a second voltage, wherein the source line is directly coupled to an elongated body region of the string, the second voltage being different than the first voltage. - View Dependent Claims (2, 3, 4, 5)
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6. A method for programming a memory cell string, comprising:
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biasing a plurality of gates to a first voltage; biasing a selected gate for programming to a second voltage; biasing a source line to a third voltage, wherein the source line is directly coupled to an elongated body region of the string, the second voltage being different than the first voltage. - View Dependent Claims (7, 8, 9)
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10. A method of operating a memory device, the method comprising:
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biasing a data line to a first potential, where the data line is coupled to a first end of a first string of memory cells and to a first end of a second string of memory cells; biasing a source to a second potential substantially the same as the first potential, where the source is coupled to a second end of the first string and to a second end of the second string of memory cells; deactivating a select gate coupled between the first end of the second string of memory cells and the data line; and performing a programming operation on a selected memory cell of the first string of memory cells concurrently with biasing the data line to the first potential and the source to the second potential and while the select gate is deactivated. - View Dependent Claims (11, 12, 13, 14, 15)
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16. A method of operating an array of memory cells, the method comprising:
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applying a potential to a data line, where the data line is coupled to a first end of a first string of memory cells and to a first end of a second string of memory cells; applying substantially the same potential to a source, where the source is coupled to a second end of the first string of memory cells and to a second end of the second string of memory cells; activating a first select gate coupled between the first end of the first string of memory cells and the data line; deactivating a second select gate coupled between the first end of the second string of memory cells and the data line; and applying a programming potential to a selected memory cell of the first string of memory cells configured to increase a threshold voltage of the selected memory cell; wherein the programming potential is applied concurrently with applying substantially the same potential to the data line and source and with activating the first select gate and deactivating the second select gate. - View Dependent Claims (17, 18, 19, 20)
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Specification