TECHNIQUES FOR RATE GOVERNING OF A DISPLAY DATA STREAM

• US 20140297902A1
• Filed: 12/21/2011
• Published: 10/02/2014
• Est. Priority Date: 12/21/2011
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Witter, Todd M., Ansari, Nausheen
• Granted Patent: US 9,304,731 B2
• Time in Patent Office: Days
• US Class Current: 710/29
• CPC Class Codes: G06F 13/385 for adaptation of a particular data processing system to different peripheral devices
• CPC Class Codes: G06F 3/03 Arrangements for converting the position or the displacement of a member into a coded form
• CPC Class Codes: G06F 3/1423 controlling a plurality of local displays, e.g. CRT and flat panel display
• CPC Class Codes: G09G 2354/00 Aspects of interface with display user
• CPC Class Codes: G09G 2370/10 Use of a protocol of communication by packets in interfaces along the display data pipeline
• CPC Class Codes: G09G 2370/20 Details of the management of multiple sources of image data
• CPC Class Codes: G09G 5/00 Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators image data processing or generation, in general G06T
• CPC Class Codes: G09G 5/006 Details of the interface to the display terminal specific for a display terminal using a CRT G09G1/167; using a flat panel G09G3/2096; circuits for interfacing with colour displays G09G5/04
• CPC Class Codes: G09G 5/363 Graphics controllers
• CPC Class Codes: H04L 47/10 Flow control; Congestion control
• CPC Class Codes: H04L 47/30 in combination with information about buffer occupancy at either end or at transit nodes
• CPC Class Codes: H04L 9/40 Network security protocols
• CPC Class Codes: H04N 17/04 for receivers

Abstract

Techniques for rate governing of a display data stream are described. In one embodiment, for example, an apparatus may comprise a processor circuit and a graphics management module comprising a differential analyzer. In some embodiments, the graphics management module may be operative on the processor circuit to determine a target display data transmission rate for one or more displays, determine, by the differential analyzer, an actual display data transmission rate for one or more display data packets based on the target display data transmission rate, transmit the one or more display data packets based on the actual display data transmission rate, and accumulate a difference between the actual display data transmission rate and the target display data transmission rate for the one or more display data packets. Other embodiments are described and claimed.

Claims

1. A method, comprising:

determining, by a processor circuit, a target display data transmission rate for one or more displays;

generating, by a digital differential analyzer (DDA) communicatively coupled to the processor circuit, an actual display data transmission rate for one or more display data packets based on the target display data transmission rate;

transmitting the one or more display data packets based on the actual display data transmission rate; and

accumulating a difference between the actual display data transmission rate and the target display data transmission rate for the one or more display data packets.

2. The method of claim 1, comprising:

determining an allocated slot quantity based on the target display data transmission rate; and

generating the actual display data transmission rate based on the allocated slot quantity.

3. The method of claim 2, the transmission of each of the one or more display data packets comprising:

adding the allocated slot quantity to a rate governing slot counter; and

setting a DDA slot counter equal to the actual display data transmission rate.

4. The method of claim 3, the transmission of each of the one or more display data packets comprising:

in an iterative loop, transmitting a next display data element comprised within a next display data slot in the display data packet, decrementing the DDA slot counter by one, and decrementing the rate governing slot counter by one, until the DDA slot counter is equal to zero; and

when the rate governing slot counter is not less than one, iteratively transmitting a rate governing data element and decrementing the rate governing slot counter by one, until the rate governing slot counter is less than one.

5. The method of claim 1, the one or more display data packets comprising a display data packet stream, the display data packet stream comprising one or more display data transmission lanes, the target display data transmission rate determined based on a number of display data transmission lanes in the display data packet stream.

6. The method of claim 5, each of the one or more display data packets comprising at least one display data payload for each of the one or more display data transmission lanes.

7. The method of claim 6, comprising:

receiving one or more display data source streams; and

processing the one or more display data source streams to form the display data packet stream, each of the one or more display data transmission lanes in the display data packet stream corresponding to a different one of the one or more display data source streams.

8. The method of claim 7, the one or more display data source streams received at a first data rate defined by a display data source stream clock signal, the first data rate differing from a display data consumption rate of the one or more displays.

9. The method of claim 8, comprising transmitting the display data packet stream at a second data rate that differs from the first data rate and matches the display data consumption rate of the one or more displays.

10. An article comprising a computer-readable storage medium containing instructions that when executed by a processor cause a computing system to:

determine a target display data transmission rate for one or more displays;

determine, by a digital differential analyzer (DDA), an actual display data transmission rate for one or more display data packets based on the target display data transmission rate;

monitor transmission of the one or more display data packets based on the actual display data transmission rate; and

accumulate a difference between the actual display data transmission rate and the target display data transmission rate for the one or more display data packets.

11. The article of claim 10, the computer-readable storage medium containing instructions that when executed cause the computing system to:

determine an allocated slot quantity based on the target display data transmission rate; and

generate the actual display data transmission rate based on the allocated slot quantity.

12. The article of claim 11, the transmission of each of the one or more display data packets comprising:

adding the allocated slot quantity to a rate governing slot counter; and

setting a DDA slot counter equal to the actual display data transmission rate.

13. The article of claim 12, the transmission of each of the one or more display data packets comprising:

in an iterative loop, transmitting a next display data element comprised within a next display data slot in the display data packet, decrementing the DDA slot counter by one, and decrementing the rate governing slot counter by one, until the DDA slot counter is equal to zero; and

when the rate governing slot counter is not less than one, iteratively transmitting a rate governing data element and decrementing the rate governing slot counter by one, until the rate governing slot counter is less than one.

14. The article of claim 10, the one or more display data packets comprising a display data packet stream, the display data packet stream comprising one or more display data transmission lanes, the target display data transmission rate determined based on a number of display data transmission lanes in the display data packet stream.

15. The article of claim 14, each of the one or more display data packets comprising at least one display data payload for each of the one or more display data transmission lanes.

16. The article of claim 15, the computer-readable storage medium containing instructions that when executed cause the computing system to:

receive one or more display data source streams at a first data rate defined by a display data source stream clock signal, the first data rate differing from a display data consumption rate of the one or more displays;

process the one or more display data source streams to form the display data packet stream, each of the one or more display data transmission lanes in the display data packet stream corresponding to a different one of the one or more display data source streams; and

monitor transmission of the display data packet stream at a second data rate that differs from the first data rate and matches the display data consumption rate of the one or more displays.

17. An apparatus, comprising:

a processor circuit; and

a graphics management module comprising a digital differential analyzer (DDA), the graphics management module operative on the processor circuit to;

determine a target display data transmission rate for one or more displays;

generate, by the DDA, an actual display data transmission rate for one or more display data packets based on the target display data transmission rate;

transmit the one or more display data packets based on the actual display data transmission rate; and

accumulate a difference between the actual display data transmission rate and the target display data transmission rate for the one or more display data packets.

18. The apparatus of claim 17, the graphics management module operative on the processor circuit to:

determine an allocated slot quantity based on the target display data transmission rate; and

generate the actual display data transmission rate based on the allocated slot quantity.

19. The apparatus of claim 18, the transmission of each of the one or more display data packets comprising:

adding the allocated slot quantity to a rate governing slot counter; and

setting a DDA slot counter equal to the actual display data transmission rate.

20. The apparatus of claim 19, the transmission of each of the one or more display data packets comprising:

in an iterative loop, transmitting a next display data element comprised within a next display data slot in the display data packet, decrementing the DDA slot counter by one, and decrementing the rate governing slot counter by one, until the DDA slot counter is equal to zero; and

when the rate governing slot counter is not less than one, iteratively transmitting a rate governing data element and decrementing the rate governing slot counter by one, until the rate governing slot counter is less than one.

21. The apparatus of claim 17, the one or more display data packets comprising a display data packet stream, the display data packet stream comprising one or more display data transmission lanes, the target display data transmission rate determined based on a number of display data transmission lanes in the display data packet stream.

22. The apparatus of claim 21, each of the one or more display data packets comprising at least one display data payload for each of the one or more display data transmission lanes.

23. The apparatus of claim 22, the graphics management module operative on the processor circuit to:

receive one or more display data source streams at a first data rate defined by a display data source stream clock signal, the first data rate differing from a display data consumption rate of the one or more displays;

process the one or more display data source streams to form the display data packet stream, each of the one or more display data transmission lanes in the display data packet stream corresponding to a different one of the one or more display data source streams; and

transmit the display data packet stream at a second data rate that differs from the first data rate and matches the display data consumption rate of the one or more displays.

24. A system, comprising:

a processor circuit;

an audio device communicatively coupled to the processor circuit; and

a graphics management module comprising a digital differential analyzer (DDA), the graphics management module operative on the processor circuit to;

determine a target display data transmission rate for one or more displays;

generate, by the DDA, an actual display data transmission rate for one or more display data packets based on the target display data transmission rate;

transmit the one or more display data packets based on the actual display data transmission rate; and

accumulate a difference between the actual display data transmission rate and the target display data transmission rate for the one or more display data packets.

25. The system of claim 24, the graphics management module operative on the processor circuit to:

determine an allocated slot quantity based on the target display data transmission rate; and

generate the actual display data transmission rate based on the allocated slot quantity.

26. The system of claim 25, the transmission of each of the one or more display data packets comprising:

adding the allocated slot quantity to a rate governing slot counter; and

setting a DDA slot counter equal to the actual display data transmission rate.

27. The system of claim 26, the transmission of each of the one or more display data packets comprising:

in an iterative loop, transmitting a next display data element comprised within a next display data slot in the display data packet, decrementing the DDA slot counter by one, and decrementing the rate governing slot counter by one, until the DDA slot counter is equal to zero; and

when the rate governing slot counter is not less than one, iteratively transmitting a rate governing data element and decrementing the rate governing slot counter by one, until the rate governing slot counter is less than one.

28. The system of claim 24, the one or more display data packets comprising a display data packet stream, the display data packet stream comprising one or more display data transmission lanes, the target display data transmission rate determined based on a number of display data transmission lanes in the display data packet stream.

29. The system of claim 28, each of the one or more display data packets comprising at least one display data payload for each of the one or more display data transmission lanes.

30. The system of claim 29, the graphics management module operative on the processor circuit to:

receive one or more display data source streams at a first data rate defined by a display data source stream clock signal, the first data rate differing from a display data consumption rate of the one or more displays;

process the one or more display data source streams to form the display data packet stream, each of the one or more display data transmission lanes in the display data packet stream corresponding to a different one of the one or more display data source streams; and

transmit the display data packet stream at a second data rate that differs from the first data rate and matches the display data consumption rate of the one or more displays.