CHIP INCLUDING MEMORY ELEMENT STORING HIGHER LEVEL MEMORY DATA ON A PAGE BY PAGE BASIS

• US 20140297914A1
• Filed: 03/31/2014
• Published: 10/02/2014
• Est. Priority Date: 03/05/2001
• Status: Active Grant

• Current Assignee: PACT XPP Schweiz AG
• Original Assignee: Pact XPP Technologies, AG
• Inventors: Vorbach, Martin
• Granted Patent: US 9,436,631 B2
• Time in Patent Office: Days
• US Class Current: 710/308
• CPC Class Codes: G06F 12/0848 Partitioned cache, e.g. separate instruction and operand caches
• CPC Class Codes: G06F 13/28 using burst mode transfer, e.g. direct memory access DMA, cycle steal G06F13/32 takes precedence
• CPC Class Codes: G06F 13/36 for access to common bus or bus system

Abstract

A bus system for transferring data between parts of a multiprocessor system. The bus system is divided into a plurality of segments. Each segment is controlled by a table providing routing information. The bus system establishes communication between a sender and a receiver according to data where the data includes an identifier that identifying the source of the data transfer and/or the target of the data transfer.

Claims

1. A bus system for transferring data between parts of a multiprocessor system, the bus system comprising:

a plurality of segments such that the bus system is divided into the plurality of segments, each of the segments are controlled by a table providing routing information;

wherein a communication between a sender and a receiver is established relating to the routing information and in accordance with a data transfer for an executed algorithm; and

at least one identifier is transmitted with the data for at least one of;

identifying the source of the data transfer; and

selecting a target of the data transfer.

2. The bus system of claim 1, wherein at least one of the parts of the multiprocessor system is a cache memory.

3. The bus system of claim 2, wherein the cache memory comprises a plurality of cache cores.

4. The bus system of claim 3, wherein the cache cores are connected to the bus system such that

for the data transfer one of the cores is selected according to an address transferred via the bus system;

wherein at least some of the plurality of cache cores are combined to form a large cache.

5. The bus system of claim 1 further comprising:

at least one buffer storing address data for performing a second data transfer if the data transfer fails.

6. The bus system of claim 5, wherein the buffer has a read pointer and a write pointer.

7. The bus system of claim 6, wherein if the data transfer fails, the read pointer is reset to the starting point of the data transfer and the second data transfer is performed.

8. The bus system of claim 1, wherein one identifier is transmitted for identifying the source of the data transfer.

9. The bus system of claim 1, wherein one identifier is transmitted for selecting the target of the data transfer.

10. The bus system of claim 1, wherein at least two identifiers are transmitted for (a) identifying the source;

and (b) selecting the target of the data transfer.

11. The bus system of claim 1, wherein the bus system connects a plurality of parts of the multiprocessor system with at least one peripheral.

12. The bus system of claim 1, wherein the bus system connects at least one part of the multiprocessor system with at least one memory.

13. The bus system of claim 1, wherein the bus system connects at least two processors.