HALF BLOCK MANAGEMENT FOR FLASH STORAGE DEVICES

• US 20140310447A1
• Filed: 09/04/2013
• Published: 10/16/2014
• Est. Priority Date: 04/15/2013
• Status: Active Grant

• Current Assignee: Macronix International Co., Ltd.
• Original Assignee: Macronix International Co., Ltd.
• Inventors: LI, HSIANG-PANG, WANG, CHENG-YUAN, CHANG, YUAN-HAO, KUO, TEI-WEI, CHANG, YU-MING, LI, YUNG-CHUN, LU, HSING-CHEN
• Granted Patent: US 9,558,108 B2
• Time in Patent Office: Days
• US Class Current: 711/103
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 2212/7205 Cleaning, compaction, garbage collection, erase control
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/16 for erasing blocks, e.g. arrays, words, groups
• CPC Class Codes: G11C 16/3427 Circuits or methods to prevent or reduce disturbance of the state of a memory cell when neighbouring cells are read or written

Abstract

A method for managing block erase operations is provided for an array of memory cells including erasable blocks of memory cells in the array. The method comprises maintaining status data for a plurality of sub-blocks of the erasable blocks of the array. The status data indicate whether the sub-blocks are currently accessible and whether the sub-blocks are invalid. The method comprises, in response to a request to erase a selected sub-block of a particular erasable block, issuing an erase command to erase the particular block if the other sub-blocks of the particular erasable block are invalid, else updating the status data to indicate that the selected sub-block is invalid.

Claims

1. An operating method for a memory, comprising:

maintaining, for an array of memory cells including erasable blocks of memory cells in the array, status data for a plurality of sub-blocks of the erasable blocks, the status data indicating whether the sub-blocks are currently accessible and whether the sub-blocks are invalid; and

in response to a request to erase a selected sub-block of a particular erasable block, updating the status data of the selected sub-block based on the status data of the other sub-block or sub-blocks of the particular erasable block.

2. The method of claim 1, including:

issuing an erase command to erase the particular erasable block if the status data indicate the other sub-block or sub-blocks of the particular erasable blocks is/are invalid, else updating the status data to indicate that the selected sub-block is invalid.

3. The method of claim 2, wherein after issuing the erase command to the array, marking the sub-blocks of the particular erasable block as free.

4. The method of claim 1, including:

if the status data indicate a pre-determined number of other sub-blocks of the particular erasable block are invalid, then copying data from any accessible sub-blocks in the particular erasable block to a different erasable block, and issuing an erase command to erase the particular erasable block, else updating the status data to indicate that the selected sub-block is invalid.

5. The method of claim 1, wherein the plurality of sub-blocks of the particular erasable block includes a first sub-block and a second sub-block, and the sub-block subject to the request is the first sub-block, then

if the second sub-block of the particular erasable block is currently accessible, marking the first sub-block of the particular erasable block as invalid;

and

if the second sub-block of the particular erasable block is currently marked as invalid, issuing the erase command to erase the first and second sub-blocks of the particular erasable block.

6. The method of claim 1, wherein the status data indicates that a sub-block of the particular block is invalid if it has been target of a request to erase when other sub-blocks of the particular block remain in-use.

7. The method of claim 1, wherein a sub-block is marked as free if the sub-block is accessible and contains no stored data.

8. The method of claim 1, wherein the array comprises NAND flash memory.

9. The method of claim 1, including address translation logic and wear leveling logic which generate requests to erase selected sub-blocks.

10. A memory apparatus comprising:

computer-readable non-transitory memory storing software executable to;

maintain, for an array of memory cells including erasable blocks of memory cells in the array, status data for a plurality of sub-blocks of the erasable blocks, the status data indicating whether the sub-blocks are currently accessible and whether the sub-blocks are invalid; and

in response to a request to erase a selected sub-block of a particular erasable block, update the status data of the selected sub-block based on the status data of the other sub-block or sub-blocks of the particular erasable block.

11. The apparatus of claim 10, wherein the software is executable to:

issue an erase command to erase the particular erasable block if the status data indicate the other sub-block or sub-blocks of the particular erasable blocks is/are invalid, else update the status data to indicate that the selected sub-block is invalid.

12. The apparatus of claim 10, wherein the software is executable, if the status data indicate a pre-determined number of other sub-blocks of the particular erasable block are invalid, to copy data from any accessible sub-blocks in the particular erasable block to a different erasable block, and issue an erase command to erase the particular erasable block, else updating the status data to indicate that the selected sub-block is invalid.

13. The apparatus of claim 10, wherein the plurality of sub-blocks of the particular erasable block includes a first sub-block and a second sub-block, and the sub-block subject to the request is the first sub-block, then

if the second sub-block of the particular erasable block is currently accessible, the software marks the first sub-block of the particular erasable block as invalid;

and

if the second sub-block of the particular erasable block is currently marked as invalid, the software issues the erase command to erase the first and second sub-blocks of the particular erasable block.

14. An apparatus comprising:

an array of memory cells including erasable blocks of memory cells in the array; and

a processor coupled to the array, including logic to;

maintain status data for a plurality of sub-blocks of the erasable blocks, the status data indicating whether the sub-blocks are currently accessible and whether the sub-blocks are invalid; and

in response to a request to erase a selected sub-block of a particular erasable block, update the status data of the selected sub-block based on the status data of the other sub-block or sub-blocks of the particular erasable block.

15. The apparatus of claim 14, wherein the processor is configured to:

issue an erase command to erase the particular erasable block if the status data indicate the other sub-block or sub-blocks of the particular erasable blocks is/are invalid, else update the status data to indicate that the selected sub-block is invalid.

16. The apparatus of claim 15, including after issuing the erase command to the array, marking the sub-blocks of the particular erasable block as free.

17. The apparatus of claim 14 wherein the processor is configured to:

if the status data indicate a pre-determined number of other sub-blocks of the particular erasable block are invalid, then copy data from any accessible sub-blocks in the particular erasable block to a different erasable block, and issue an erase command to erase the particular erasable block, else update the status data to indicate that the selected sub-block is invalid.

18. The apparatus of claim 14, wherein the plurality of sub-blocks of the particular erasable block includes a first sub-block and a second sub-block, and the sub-block subject of the request is the first sub-block, then

if the second sub-block of the particular erasable block is currently accessible, the logic marks the first sub-block of the particular erasable block as invalid;

and

if the second sub-block of the particular erasable block is currently marked as invalid, the logic issues the erase command to erase the first and second sub-blocks of the particular erasable block.

19. The apparatus claim 14, wherein the status data indicates that a sub-block of the particular block is invalid if it has been target of a request to erase when other sub-blocks of the particular block remain in-use.

20. The apparatus of claim 14, wherein the array comprises NAND flash memory.