SYSTEM AND METHOD FOR MANUFACTURING SELF-ALIGNED STI WITH SINGLE POLY
First Claim
1. A method for manufacturing a memory device, the method comprising:
- performing a shallow trench isolation process on a semiconductor material to form a plurality of active regions over the semiconductor material, the plurality of active regions having a plurality of sharp corners;
forming a plurality of isolation regions separating the plurality of active regions, the plurality of sharp corners of the plurality of active regions being exposed during the forming of the plurality of isolation regions;
rounding the plurality of sharp corners;
filling the plurality of isolation regions with an insulator material;
forming a plurality of charge trapping structures over the plurality of active regions, wherein the plurality of charge trapping structures are self-aligned, are separated from each other, and wherein each charge trapping structure corresponds specifically to a different active region of the plurality of active regions; and
forming a first layer of semiconductor or conductive material over the charge trapping structure.
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Abstract
A method for fabricating a memory device with a self-aligned trap layer and rounded active region corners is disclosed. In the present invention, an STI process is performed before any of the charge-trapping and top-level layers are formed. Immediately after the STI process, the sharp corners of the active regions are exposed. Because these sharp corners are exposed at this time, they are available to be rounded through any number of known rounding techniques. Rounding the corners improves the performance characteristics of the memory device. Subsequent to the rounding process, the charge-trapping structure and other layers can be formed by a self-aligned process.
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Citations
20 Claims
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1. A method for manufacturing a memory device, the method comprising:
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performing a shallow trench isolation process on a semiconductor material to form a plurality of active regions over the semiconductor material, the plurality of active regions having a plurality of sharp corners; forming a plurality of isolation regions separating the plurality of active regions, the plurality of sharp corners of the plurality of active regions being exposed during the forming of the plurality of isolation regions; rounding the plurality of sharp corners; filling the plurality of isolation regions with an insulator material; forming a plurality of charge trapping structures over the plurality of active regions, wherein the plurality of charge trapping structures are self-aligned, are separated from each other, and wherein each charge trapping structure corresponds specifically to a different active region of the plurality of active regions; and forming a first layer of semiconductor or conductive material over the charge trapping structure. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12)
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13. A system comprising:
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a processor; a bus coupled to the processor; a non-volatile memory coupled to the bus, wherein the non-volatile memory comprises; a semiconductor substrate; a plurality of active regions disposed over the semiconductor substrate, each active region of the plurality of active regions having a plurality of sharp corners; a plurality of trenches separating the plurality of active regions and filled with an insulator material, the plurality of sharp corners of the plurality of active regions being exposed by a formation of the plurality of trenches; and a plurality of self-aligned charge trapping structures disposed over the plurality of active regions, the plurality of self-aligned charge trapping structures being separated from each other, each self-aligned charge trapping structure corresponding specifically to a different active region of the plurality of active regions, wherein the plurality of sharp corners of the plurality of active regions are rounded by the rounding process before the plurality of trenches are filled with the insulator material and the plurality of self-aligned charge trapping structures are formed. - View Dependent Claims (14, 15, 16, 17, 18, 19, 20)
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Specification