SEMICONDUCTOR PACKAGE
First Claim
1. A semiconductor package, comprising:
- a package substrate which comprises a power supply region and an interconnection region around the power supply region;
a plurality of ground terminals and a plurality of power terminals, which are disposed in the power supply region with a dielectric interposed between the ground terminals and the power terminals, wherein the ground terminals and the power terminals extend from a top surface of the package substrate to a bottom surface of the package substrate; and
at least one semiconductor chip mounted on the package substrate comprising a plurality of ground pads which are commonly connected to a ground terminal of the ground terminals and a plurality of power pads which are commonly connected to a power terminal of the power terminals.
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Accused Products
Abstract
Provided is a semiconductor package which may include a package substrate which includes a power supply region and an interconnection region around the power supply region, a plurality of ground terminals and a plurality of power terminals, which are disposed in the power supply region with a dielectric interposed between the ground terminals and the power terminals, wherein the ground terminals and the power terminals extend from a top surface of the package substrate to a bottom surface of the package substrate, and at least one semiconductor chip mounted on the package substrate, the semiconductor chip includes a plurality of ground pads which are commonly connected to a ground terminal of the ground terminals and a plurality of power pads which are commonly connected to a power terminal of the power terminals.
20 Citations
20 Claims
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1. A semiconductor package, comprising:
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a package substrate which comprises a power supply region and an interconnection region around the power supply region; a plurality of ground terminals and a plurality of power terminals, which are disposed in the power supply region with a dielectric interposed between the ground terminals and the power terminals, wherein the ground terminals and the power terminals extend from a top surface of the package substrate to a bottom surface of the package substrate; and at least one semiconductor chip mounted on the package substrate comprising a plurality of ground pads which are commonly connected to a ground terminal of the ground terminals and a plurality of power pads which are commonly connected to a power terminal of the power terminals. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11. A package substrate, comprising:
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a substrate comprising a top surface on which a semiconductor chip is mounted, wherein the substrate further comprises a power supply region and an interconnection region around the power supply region; a plurality of inner interconnection lines disposed in the interconnection region of the substrate to transmit external signals to the semiconductor chip; a ground terminal disposed in the power supply region of the substrate, and which extends from the top surface of the substrate to a bottom surface of the substrate; and a power terminal disposed in the power supply region of the substrate, wherein the power terminal is disposed at one side of the ground terminal with a dielectric interposed between the power terminal and the ground terminal such that the power terminal is electrically coupled with the ground terminal. - View Dependent Claims (12, 13, 14, 15)
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16. A semiconductor package, comprising:
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a package substrate which comprises a power supply region and an interconnection region; a ground terminal disposed in the power supply region; a first power terminal disposed in the power supply region and at one side of the ground terminal with a dielectric disposed between the first power terminal and the ground terminal; a second power terminal disposed in the power supply region and at another side of the ground terminal with the dielectric disposed between the second power terminal and the ground terminal; and a first semiconductor chip and a second semiconductor chip, which are mounted on the package substrate, wherein the interconnection region surrounds the power supply region, wherein the first semiconductor chip is connected to the first power terminal and the ground terminal, and wherein the second semiconductor chip is connected to the second power terminal and the ground terminal. - View Dependent Claims (17, 18, 19, 20)
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Specification