METHOD AND COMPOSITION FOR ELECTRODEPOSITION OF COPPER IN MICROELECTRONICS WITH DIPYRIDYL-BASED LEVELERS

• US 20140322912A1
• Filed: 07/08/2014
• Published: 10/30/2014
• Est. Priority Date: 11/26/2008
• Status: Active Grant

• Current Assignee: MacDermid Enthone Inc. (Element Solutions Inc)
• Original Assignee: Enthone Incorporated (Element Solutions Inc)
• Inventors: Paneccasio, Vincent Jr., Lin, Xuan, Hurtubise, Richard, Chen, Qingyun
• Granted Patent: US 9,613,858 B2
• Time in Patent Office: Days
• US Class Current: 438/675
• CPC Class Codes: C25D 3/38 of copper
• CPC Class Codes: C25D 5/02 Electroplating of selected surface areas
• CPC Class Codes: C25D 7/123 Semiconductors first coated with a seed layer or a conductive layer
• CPC Class Codes: H01L 21/2885 using an external electrical current, i.e. electro-deposition
• CPC Class Codes: H01L 21/76877 Filling of holes, grooves or trenches, e.g. vias, with conductive material
• CPC Class Codes: H01L 21/76879 by selective deposition of conductive material in the vias, e.g. selective C.V.D. on semiconductor material, plating plating on semiconductors in general H01L21/288
• CPC Class Codes: H01L 23/53228 the principal metal being copper
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A method and composition for metallizing a via feature in a semiconductor integrated circuit device substrate, using a leveler compound which is a dipyridyl compound.

Claims

1. A method for metalizing a via feature in a semiconductor integrated circuit device substrate, wherein the semiconductor integrated circuit device substrate comprises a front surface, a back surface, and the via feature and wherein the via feature comprises an opening in the front surface of the substrate, a sidewall extending from the front surface of the substrate inward, and a bottom, the method comprising:

contacting the semiconductor integrated circuit device substrate with an electrolytic copper deposition chemistry comprising (a) a source of copper ions and (b) a leveler compound, wherein the leveler compound comprises a polymer comprising repeating units that comprise quaternized dipyridyl moieties; and

supplying electrical current to the electrolytic deposition chemistry to deposit copper metal onto the bottom and sidewall of the via feature, thereby yielding a copper filled via feature.

4. A method as set forth in claim 1 wherein said leveler compound comprises the reaction product of a dipyridyl compound and an alkylating agent, wherein the dipyridyl compound comprises structure (IIf):

2. A method as set forth in claim 2 wherein said leveler compound has been formed by co-polymerization of a dipyridyl compound and an alkylating agent and repeat units of the polymer comprise one moiety derived from the dipyridyl compound and one moiety derived from the alkylating agent.

3. A method as set forth in claim 2 wherein said composition further comprises:

(c) an accelerator; and

(d) a suppressor.

5. A composition for metalizing a via feature in a semiconductor integrated circuit device substrate comprising:

(a) a source of copper ions;

(b) a leveler compound, wherein the leveler compound comprises a polymer comprising the following general structure (IV);

6. A composition as set forth in claim 5 wherein the leveler compound comprises a polymer having the following general structure (V):

7. A composition as set forth in claim 5 wherein the leveler compound is selected from the group consisting of:

(i) a polymer comprising the following structure (VI);

8. A composition as set forth in claim 5 wherein the leveler compound comprises a polymer comprising the following general structure (VII):

9. A composition as set forth in claim 5 wherein the leveler compound comprises a polymer comprising the following structure (VIII):

10. A composition for metalizing a via feature in a semiconductor integrated circuit device substrate comprising:

(a) a source of copper ions;

(b) a leveler compound, the leveler compound comprises the following general structure (XIII);

11. A composition as set forth in claim 10 wherein the leveler compound comprises the following general structure (XVI):

12. A composition as set forth in claim 10 wherein the leveler compound comprises the following structure (XVII):

13. A composition as set forth in claim 10 wherein the leveler compound comprises the following structure (XVIII):

14. A composition as set forth in claim 10 wherein the leveler compound comprises the following general structure (XIV):

15. A composition as set forth in claim 14 further comprising:

(a) an accelerator; and

(c) a suppressor.

16. A composition as set forth in claim 10 wherein the leveler compound comprises the following general structure (XV):

17. A composition as set forth in claim 16 further comprising:

(a) an accelerator; and

(c) a suppressor.