SEMICONDUCTOR DEVICE

• US 20140335667A1
• Filed: 07/24/2014
• Published: 11/13/2014
• Est. Priority Date: 03/12/2008
• Status: Active Grant

• Current Assignee: Infineon Technologies AG
• Original Assignee: Infineon Technologies AG
• Inventors: Zundel, Markus
• Granted Patent: US 9,287,373 B2
• Time in Patent Office: Days
• US Class Current: 438/197
• CPC Class Codes: H01L 29/40114 the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/41741 for vertical or pseudo-vertical devices
• CPC Class Codes: H01L 29/42372 characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out H01L29/42324 takes precedence
• CPC Class Codes: H01L 29/4238 characterised by the surface lay-out
• CPC Class Codes: H01L 29/66477 with an insulated gate, i.e. MISFET
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A semiconductor device includes an active area having a source and a gate. A gate metal contact is deposited above and forms an electrical contact with the gate and a source metal contact is deposited above and forms an electrical contact with the source. The source metal contact includes a plurality of metal through contacts positioned adjacent a side of the active area, the plurality of metal through contacts being spaced at intervals from one another and arranged in two or more rows.

Claims

1. A method of making a semiconductor device comprising:

providing an active area comprising a source and a gate;

depositing a gate metal contact above and forming an electrical contact with the gate; and

depositing a source metal contact above and forming an electrical contact with the source and comprising a plurality of metal through contacts positioned adjacent a side of the active area, the plurality of metal through contacts being spaced at intervals from one another and arranged in two or more rows.

2. The semiconductor device of claim 1, comprising disposing an electrically insulating layer between the source metal contact and the source and between the gate metal contact and the gate and wherein the metal through contacts extend through the electrically insulating layer and are disposed on the source.

3. The semiconductor device of claim 1 wherein in plan view, the metal through contacts are elongate, the longer direction being arranged generally parallel to the side of the source metal contact.

4. The semiconductor device of claim 1, comprising offsetting the metal through contacts of adjacent rows with respect to one another.

5. The semiconductor device of claim 1, wherein in plan view, forming the metal through contacts to be generally funnel-shaped.

6. The semiconductor device of claim 1, wherein one or more rows of metal through contacts comprise metal through contacts comprising a generally rectangular shape in plan view and one or two rows of metal through contacts comprise metal through contacts comprising a generally funnel-shape in plan view.