SECOND ORDER HARMONIC CANCELLATION FOR RADIO FREQUENCY FRONT-END SWITCHES

• US 20140335802A1
• Filed: 05/08/2014
• Published: 11/13/2014
• Est. Priority Date: 05/08/2013
• Status: Active Grant

• Current Assignee: Skyworks Solutions Incorporated
• Original Assignee: RFaxis, Inc. (Skyworks Solutions Incorporated)
• Inventors: LI, Qiang, ZHAO, Huan
• Granted Patent: US 9,749,003 B2
• Time in Patent Office: Days
• US Class Current: 455/83
• CPC Class Codes: H04B 1/48 in circuits for connecting transmitter and receiver to a common transmission path, e.g. by energy of transmitter H04B1/46 takes precedence
• CPC Class Codes: H04B 2001/485 inhibiting unwanted transmission

Abstract

A radio frequency switch circuit with improved harmonic suppression and low insertion loss has an antenna port and a plurality of signal ports. A plurality of transistor switch circuits, are connected to a respective one of the plurality of signal ports and to the antenna port. Each of the transistor switch circuits has a transistor, which in an off state, together with a harmonic suppression capacitor and a parallel inductor both connected thereto, define a tank circuit that suppresses RF signals applied to the corresponding transistor switch circuit from a different one of the transistor switch circuits. The harmonic suppression capacitor is tuned to distribute large signal voltage swings in the RF signal amongst parasitic diodes of the transistor.

Claims

1. A radio frequency (RF) switch circuit, comprising:

an antenna port;

a plurality of signal ports;

a plurality of transistor switch circuits each connected to a respective one of the plurality of signal ports and to the antenna port, each of the transistor switch circuits including a transistor which in an off state, together with a harmonic suppression capacitor and a parallel inductor both connected thereto, define a tank circuit that suppresses RF signals applied to the corresponding transistor switch circuit from a different one of the transistor switch circuits;

wherein the harmonic suppression capacitor is tuned to distribute large signal voltage swings in the RF signal amongst parasitic diodes of the transistor.

2. The RF switch circuit of claim 1, wherein each of the transistor switch circuits includes a transistor activation suppression capacitor connected to the transistor and the signal port.

3. The RF switch circuit of claim 2, wherein the transistor activation suppression capacitor is connected across a source and a gate of the transistor.

4. The RF switch circuit of claim 2, wherein the transistor activation suppression capacitor is tuned to maximize peak power handling capacity of the transistor switch circuit.

5. The RF switch circuit of claim 1, wherein the transistor is defined by a gate, a source, a drain, and a body.

6. The RF switch circuit of claim 5, wherein the harmonic suppression capacitor is connected to the body and to the drain of the transistor.

7. The RF switch circuit of claim 5, wherein the inductor is connected to the source and to the drain of the transistor.

8. The RF switch circuit of claim 5, wherein:

a first one of the parasitic diodes of the transistor is between the body and the drain thereof; and

a second one of the parasitic diodes of the transistor is between the body and the source thereof.

9. The RF switch circuit of claim 1, wherein each of the transistor switches define a minimal series resistance with the transistor thereof in an on state.

10. The RF switch circuit of claim 1, further comprising:

a direct current blocking capacitor connected between each of the transistor switch circuits and the antenna port.

11. The RF switch circuit of claim 1, further comprising:

a direct current blocking capacitor connected between each of the transistor switch circuits and the respective signal ports.

12. The RF switch circuit of claim 1, wherein the transistors have an n-type metal oxide semiconductor (N-MOS) field effect structure.

13. The RF switch circuit of claim 1, wherein the signal ports and the transistor switch circuits number three to define a single pole, triple throw switch.

14. An RF single pole, triple throw switch, comprising:

a common pole terminal;

a first signal terminal;

a first control line terminal;

a first transistor with a body, a source connected to the first signal terminal, a drain connected to the common pole terminal, and a gate connected to the first control line terminal, the first transistor being selectively activatable in response to a first enable signal applied to the first control line terminal;

a first transistor harmonic suppression capacitor connected across the body and the drain of the first transistor;

a first inductor connected to the source and the drain of the first transistor, the first inductor and the first transistor harmonic suppression capacitor defining a first tank circuit with the first transistor in a deactivated state, the first tank circuit blocking RF signals on the drain of the first transistor;

a second signal terminal;

a second control line terminal;

a second transistor with a body, a source connected to the second signal terminal, a drain connected to the common pole terminal, and a gate connected to the second control line terminal, the second transistor being selectively activatable in response to a second enable signal applied to the first control line terminal;

a second transistor harmonic suppression capacitor connected across the body and the drain of the second transistor;

a second inductor connected to the source and the drain of the second transistor, the second inductor and the second harmonic suppression capacitor defining a second tank circuit with the second transistor in a deactivated state, the second tank circuit blocking RF signals on the drain of the second transistor;

a third signal terminal;

a third control line terminal;

a third transistor with a body, a source connected to the third signal terminal, a drain connected to the common pole terminal, and a gate connected to the third control line terminal, the third transistor being selectively activatable in response to a third enable signal applied to the third control line terminal;

a third transistor harmonic suppression capacitor connected across the body and the drain of the third transistor; and

a third inductor connected to the source and the drain of the third transistor, the third inductor and the third harmonic suppression capacitor defining a third tank circuit with the third transistor in a deactivated state, the third tank circuit blocking RF signals on the drain of the third transistor.

15. The switch of claim 14, further comprising:

a first transistor activation suppression capacitor connected across the gate and the source of the first transistor;

a second transistor activation suppression capacitor connected across the gate and the source of the second transistor; and

a third transistor activation suppression capacitor connected across the gate and the source of the third transistor.

16. The switch of claim 15, wherein each of the transistor activation suppression capacitor are tuned to maximize peak power handling capacity of the respective transistor.

17. The switch of claim 14, wherein:

the first harmonic suppression capacitor is tuned to distribute large signal voltage swings in the RF signal amongst parasitic diodes of the first transistor;

the second harmonic suppression capacitor is tuned to distribute large signal voltage swings in the RF signal amongst parasitic diodes of the second transistor; and

the third harmonic suppression capacitor is tuned to distribute large signal voltage swings in the RF signal amongst parasitic diodes of the third transistor.

18. The switch of claim 14, further comprising:

a first direct current blocking capacitor connected between the drain of the first transistor and the common pole terminal;

a second direct current blocking capacitor connected between the drain of the second transistor and the common pole terminal; and

a third direct current blocking capacitor connected between the drain of the third transistor and the common pole terminal.

19. The RF switch circuit of claim 14, further comprising:

a first direct current blocking capacitor connected between the first signal terminal and the source of the first transistor;

a second direct current blocking capacitor connected between the second signal terminal and the source of the second transistor; and

a third direct current blocking capacitor connected between the third signal terminal and the source of the third transistor.

20. The switch of claim 14, wherein the first transistor, the second transistor, and the third transistor have an n-type metal oxide semiconductor (N-MOS) field effect structure.