Semiconductor Device with a Field Plate Double Trench Having a Thick Bottom Dielectric

• US 20140339651A1
• Filed: 05/01/2014
• Published: 11/20/2014
• Est. Priority Date: 05/16/2013
• Status: Active Grant

• Current Assignee: Infineon Technologies Americas Corp. (Infineon Technologies AG)
• Original Assignee: International Rectifier Corporation (Infineon Technologies AG)
• Inventors: Henson, Timothy D., Kelkar, Kapil, Radic, Ljubo
• Granted Patent: US 9,735,241 B2
• Time in Patent Office: Days
• US Class Current: 257/409
• CPC Class Codes: H01L 21/283 Deposition of conductive or insulating materials for electrodes conducting electric current
• CPC Class Codes: H01L 21/3083 characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
• CPC Class Codes: H01L 21/765 by field effect H01L21/76264 takes precedence
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/66666 Vertical transistors H01L29/66712, H01L29/66742 take precedence
• CPC Class Codes: H01L 29/66674 DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region making lateral high-voltage MISFETs with channel well and drain offset region H01L29/66659
• CPC Class Codes: H01L 29/7801 DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region lateral high-voltage MISFETs with channel well and drain offset region H01L29/7835
• CPC Class Codes: H01L 29/7827 Vertical transistors H01L29/7802, H01L29/78642 take precedence

Abstract

Disclosed is a power device, such as power MOSFET, and method for fabricating same. The device includes an upper trench situated over a lower trench, where the upper trench is wider than the lower trench. The device further includes a trench dielectric inside the lower trench and on sidewalls of the upper trench. The device also includes an electrode situated within the trench dielectric. The trench dielectric of the device has a bottom thickness that is greater than a sidewall thickness.

Claims

1. A power semiconductor device comprising:

an upper trench situated over a lower trench, said upper trench being wider than said lower trench;

a trench dielectric situated inside said lower trench and on sidewalls of said upper trench;

an electrode situated within said trench dielectric;

a bottom thickness of said trench dielectric is greater than a sidewall thickness of said trench dielectric on said sidewalls of said upper trench.

2. The power semiconductor device of claim 1, wherein said electrode is a field plate.

3. The power semiconductor device of claim 1, wherein said lower trench is completely filled with said trench dielectric.

4. The power semiconductor device of claim 1, wherein said lower trench is partially filled with said trench dielectric.

5. The power semiconductor device of claim 1, wherein said bottom thickness is at least 120% greater than said sidewall thickness.

6. The power semiconductor device of claim 1, wherein said sidewall thickness tapers from a top to a bottom of said sidewalls.

7. The power semiconductor device of claim 1, wherein said trench dielectric comprises TEOS.

8. A power MOSFET comprising:

a field plate trench situated over a lower trench, said field plate trench being wider than said lower trench;

a trench dielectric situated inside said lower trench and on sidewalls of said field plate trench;

a field plate situated within said trench dielectric;

a bottom thickness of said trench dielectric is greater than a sidewall thickness of said trench dielectric on said sidewalls of said field plate trench.

9. The power MOSFET of claim 8, wherein said lower trench is completely filled with said trench dielectric.

10. The power MOSFET of claim 8, wherein said lower trench is partially filled with said trench dielectric.

11. The power MOSFET of claim 8, wherein said bottom thickness is at least 120% greater than said sidewall thickness.

12. The power MOSFET of claim 8, wherein said sidewall thickness tapers from a top to a bottom of said sidewalls.

13. The power MOSFET of claim 8, wherein said trench dielectric comprises TEOS.

14. A method of fabricating a power semiconductor device, said method comprising:

forming an upper trench in a substrate;

forming a lower trench in said substrate, said upper trench being wider than said lower trench;

forming a trench dielectric in said lower trench and on sidewalls of said upper trench;

forming an electrode within said trench dielectric;

wherein said trench dielectric is formed such that a bottom thickness of said trench dielectric is greater than a sidewall thickness of said trench dielectric on said sidewalls of said upper trench.

15. The method of claim 14 further comprising:

forming a sacrificial layer in said upper trench prior to said forming said lower trench;

etching said sacrificial layer to form spacers on said sidewalls of said upper trench.

16. The method of claim 15 further comprising removing said spacers after said forming said lower trench.

17. The method of claim 14, wherein said lower trench is completely filled with said trench dielectric.

18. The method of claim 14, wherein said lower trench is partially filled with said trench dielectric.

19. The method of claim 14, wherein said electrode is a field plate.

20. The method of claim 14, wherein said bottom thickness is at least 120% greater than said sidewall thickness.