APPARATUSES HAVING A FERROELECTRIC FIELD-EFFECT TRANSISTOR MEMORY ARRAY AND RELATED METHOD

• US 20140340952A1
• Filed: 05/17/2013
• Published: 11/20/2014
• Est. Priority Date: 05/17/2013
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Ramaswamy, D. V. Nirmal, Johnson, Adam D.
• Granted Patent: US 9,281,044 B2
• Time in Patent Office: Days
• US Class Current: 365/51
• CPC Class Codes: G11C 11/22 using ferroelectric elements
• CPC Class Codes: G11C 11/221 using ferroelectric capacitors
• CPC Class Codes: G11C 11/223 using MOS with ferroelectric gate insulating film
• CPC Class Codes: G11C 11/2255 Bit-line or column circuits
• CPC Class Codes: G11C 11/2257 Word-line or row circuits
• CPC Class Codes: H01L 29/78391 the gate comprising a layer which is used for its ferroelectric properties
• CPC Class Codes: H10B 51/20 characterised by the three-dimensional arrangements, e.g. with cells on different height levels

Abstract

An apparatus comprises field-effect transistor (FET) structures stacked horizontally and vertically in a three-dimensional memory array architecture, gates extending vertically and spaced horizontally between the plurality of FET structures, and a ferroelectric material separating the FET structures and the gates. Individual ferroelectric FETs (FeFETs) are formed at intersections of the FET structures, the gates, and the ferroelectric material. Another apparatus comprises a plurality of bit lines and word lines. Each bit line has at least two sides that are coupled with a ferroelectric material such that each bit line is shared by neighboring gates to faun a plurality of FeFETs. A method of operating a memory array comprises applying a combination of voltages to a plurality of word lines and digit lines for a desired operation for a plurality of FeFET memory cells, at least one digit line having plurality of FeFET memory cells accessible by neighboring gates.

Claims

1. An apparatus, comprising:

a plurality of field-effect transistor (FET) structures stacked horizontally and vertically in a three-dimensional memory array architecture;

a plurality of gates extending vertically and spaced horizontally between the plurality of FET structures; and

a ferroelectric material separating the plurality of FET structures and the plurality of gates, wherein individual ferroelectric FETs (FeFETs) are formed at intersections the plurality of FET structures, the plurality of gates, and the ferroelectric material.

2. The apparatus of claim 1, wherein each FET structure of the plurality of FET structures includes a drain region, a body region, and a source region stacked in a vertical arrangement.

3. The apparatus of claim 2, further comprising a plurality of access lines coupled with individual FeFETs.

4. The apparatus of claim 3, wherein the plurality of access lines includes:

a plurality of word lines coupled to the plurality of gates; and

a plurality of bit lines coupled to the drain regions of the plurality of FET structures.

5. The apparatus of claim 4, wherein the plurality of word lines couple to the plurality of gates according to an alternating contact scheme.

6. The apparatus of claim 2, wherein each FET structure further comprises:

a drain contact coupled to the drain region; and

a source contact coupled to the source region, wherein the drain contact and the source contact are coupled on opposite ends of the three-dimensional memory array architecture.

7. The apparatus of claim 6, wherein the source contact is further coupled to the body region of the corresponding FET structure.

8. The apparatus of claim 1, wherein each gate of the plurality of gates have the ferroelectric material disposed on at least one side of the gate.

9. The apparatus of claim 1, wherein at least some of the gates of the plurality of gates have the ferroelectric material disposed on at least two sides of the gate.

20. The apparatus of claim 9, wherein the first vertical FeFET stack and the second vertical FeFET stack comprise a portion of a three-dimensional memory array of the apparatus.

21. The apparatus of claim 20, wherein the three-dimensional memory array comprises at least a portion of a memory device of the apparatus.

22. The apparatus of claim 21, wherein the memory device comprises at least a portion of the apparatus.

23. The apparatus of claim 22, further comprising a control circuit operably coupled to the memory device, and configured to apply one or more voltages to perform operations on memory cells of the first vertical FeFET stack and the second vertical FeFET stack.

24. The apparatus of claim 23, further comprising an input device and an output device operably coupled to the control circuit.

10. An apparatus, comprising:

a first vertical ferroelectric field-effect transistor (FeFET) stack including a first plurality gates separated from a first FET structure by a first ferroelectric material; and

a second vertical FeFET stack including a second plurality gates separated from a second FET structure by a second ferroelectric material, wherein the first vertical FeFET stack and the second FeFET stack are stacked horizontally and separated by a dielectric material.

11. The apparatus of claim 10, wherein the dielectric material includes a third ferroelectric material configured such that the second vertical FeFET stack has memory cells on both sides of the second FET structure of the second vertical FeFET stack.

12. The apparatus of claim 11, wherein neighboring gates from the first plurality of gates and the second plurality of gates along the same horizontal axis are part of the same word line.

13. The apparatus of claim 12, further comprising a plurality of word line parallel contacts that extend linearly across the first vertical FeFET stack and the second FeFET stack, wherein a single word line contact couples the neighboring gates from the first plurality of gates and the second plurality of gates along the same horizontal axis.

14. The apparatus of claim 11, wherein neighboring gates from the first plurality of gates and the second plurality of gates along the same horizontal axis are part of different word lines.

15. The apparatus of claim 14, further comprising a plurality of additional vertical FeFET stacks that include additional pluralities of gates, the additional vertical FeFET stacks stacked horizontally with the first vertical FeFET stack and the second vertical FeFET stack.

16. The apparatus of claim 15, further comprising a plurality of mutually parallel word line contacts that extend along the first vertical FeFET stack, the second vertical FeFET stack, and the plurality of additional vertical FeFET stacks, wherein neighboring gates from the first plurality of gates and the second plurality of gates along the same horizontal axis couple to different ones of the mutually parallel word line contacts.

17. The apparatus of claim 16, wherein:

one of the neighboring gates extends to a first end of the first vertical FeFET stack, and couples with a first one of the mutually word line contact; and

another of the neighboring gates extends to a second end of the second vertical FeFET stack, and couples with a second one of the mutually word line contact.

18. The apparatus of claim 16, wherein the plurality of word line contacts are offset from the first plurality of gates and the second plurality of gates, and further extend linearly across the first vertical FeFET stack, the second vertical FeFET stack, and the plurality of additional vertical FeFET stacks.

19. The apparatus of claim 16, wherein the plurality of word line contacts each have an arcuate shape that extends around one of the neighboring gates.

25. An apparatus, comprising:

a ferroelectric field-effect transistor (FeFET) memory array having a plurality of FeFETs coupled at cross points of a plurality of access lines, wherein the FeFET memory array is configured to have a substantially uniform series resistance for a current path for each FeFET of the plurality of FeFETs.

26. The apparatus of claim 25, further comprising:

a plurality of bit line contacts coupled to bit lines of the plurality of FeFETs;

a plurality of source line contacts coupled to source lines of the plurality of FeFETs; and

a plurality of word line contacts coupled to word lines of the plurality of FeFETs, wherein the bit line contacts and the source line contacts are coupled on opposing ends of the FeFET memory array.

27. An apparatus, comprising:

a three-dimensional memory array having a plurality of ferroelectric field-effect transistor (FeFET) memory cells formed at intersections of ferroelectric material coupled with a plurality of bit lines and a plurality of word lines.

28. The apparatus of claim 27, wherein each bit line of the plurality of bit lines are coupled to a drain region that has at least two sides coupled with ferroelectric material such that each drain region is shared by neighboring gates to form the plurality of FeFET memory cells.

29. The apparatus of claim 28, wherein the neighboring gates and word lines are configured to independently access the plurality of FeFETs associated with the same bit line.

30. The apparatus of claim 27, wherein the plurality of FeFET memory cells are formed along vertical strings of the three-dimensional memory array, wherein the vertical strings couple with memory cell gates coupled with the plurality of word lines.

31. The apparatus of claim 30, wherein the vertical strings each include a vertical channel surrounded by the ferroelectric material.

32. A method of operating a three-dimensional ferroelectric field-effect transistor (FeFET) memory array, the method comprising:

applying a combination of voltages to a plurality of word lines and digit lines for a desired operation for a plurality of FeFET memory cells of a three-dimensional FeFET memory array, at least one digit line having plurality of FeFET memory cells accessible by neighboring gates.

33. The method of claim 32, wherein applying a combination of voltages comprises employing a selection scheme from the group consisting of a V/3 selection scheme and a V/2 selection scheme.