INTERRUPTION OF CHIP COMPONENT MANAGING TASKS

• US 20140344824A1
• Filed: 06/11/2014
• Published: 11/20/2014
• Est. Priority Date: 05/14/2013
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Brock, Bishop, Gloekler, Tilman, Koenig, Andreas, Lichtenau, Cedric, Lobo, Preetham M.
• Granted Patent: US 9,378,048 B2
• Time in Patent Office: Days
• US Class Current: 718/103
• CPC Class Codes: G06F 9/46 Multiprogramming arrangements
• CPC Class Codes: G06F 9/485 Task life-cycle, e.g. stopping, restarting, resuming execution G06F9/4881 takes precedence
• CPC Class Codes: G06F 9/5038 considering the execution order of a plurality of tasks, e.g. taking priority or time dependency constraints into consideration scheduling strategies G06F9/4881 and subgroups

Abstract

Embodiments include receiving, at a microcontroller of a chip, a request to execute a first task having a first priority. Embodiments further include determining that a second task having a second priority is currently executing. Embodiments further include determining that the first priority is higher than the second priority. Embodiments further include determining whether a value in a register indicates that the second task can be interrupted. If it is determined that the second task can be interrupted, embodiments further include triggering execution of the second task. If it is determined that the second task cannot be interrupted, embodiments further include waiting for lapse of a time period since receipt of the request to execute the first task, and interrupting the second task upon detecting lapse of the time period, or detecting, prior to the lapse of the time period, that the second task can be interrupted.

Claims

1. A method comprising:

receiving, at a microcontroller of a chip, a request to execute on the chip a first task having a first priority;

determining that a second task having a second priority is currently executing on the chip;

determining that the first priority is higher than the second priority;

determining whether a value in a register indicates that the second task can be interrupted without causing the chip or any components of the chip to be in one or more of an inconsistent state or a harmful state;

if the value indicates that the second task can be interrupted without causing the chip or any components of the chip to be in one or more of an inconsistent state or a harmful state,

interrupting execution of the second task and triggering execution of the first task on the chip;

if the value indicates that the second task cannot be interrupted without causing the chip or any components of the chip to be in one or more of an inconsistent state or a harmful state,

waiting for lapse of a time period since receipt of the request to execute the first task; and

interrupting the second task upon,

detecting lapse of the time period since receipt of the request to execute the first task, or

detecting, prior to lapse of the time period, that the value in the register has been changed to indicate that the second task can be interrupted without causing the chip or any components of the chip to be in one or more of an inconsistent state or a harmful state.

2. The method of claim 1, further comprising:

during the waiting for lapse of a time period since receipt of the request to execute the second task, monitoring the value in the register.

3. The method of claim 1, wherein the request to execute on a chip a first task having a first priority includes an attribute value indicating the first priority.

4. The method of claim 1, wherein the first priority and the second priority are based on a type of the first task and a type of the second task, respectively.

5. The method of claim 1, wherein the first task is one of a first group of tasks and wherein the second task is one of a second group of tasks, wherein tasks of the first group of tasks are responsible for one or more of booting a processor core of the chip, initializing a processor core of the chip, shutting down a processor core of the chip, protecting a processor core of the chip against overheating, and managing an energy supply of a processor core of the chip, and wherein tasks of the second group of tasks are responsible for monitoring a processor core of the chip, clocking a processor core of the chip, creating usage statistics for a processor core of the chip, and identifying errors and invalid states of a processor core of the chip.

6. The method of claim 1, wherein the request to execute on a chip a first task having a first priority indicates a duration for the time period.