ELEMENTAL SEMICONDUCTOR MATERIAL CONTACTFOR HIGH ELECTRON MOBILITY TRANSISTOR
First Claim
1. A semiconductor structure comprising a high electron mobility transistor (HEMT), wherein said HEMT comprises:
- a substrate comprising a stack, from bottom to top, of a substrate compound semiconductor layer and a top compound semiconductor layer;
a gate electrode contacting a horizontal surface of a portion of said top compound semiconductor layer;
a source region embedded in said substrate; and
a drain region embedded in said substrate and laterally spaced from said source region, wherein said second portion is laterally spaced from said first portion by a width of said gate electrode, and wherein each of said source region and said drain region comprises at least one elemental semiconductor material.
5 Assignments
0 Petitions
Accused Products
Abstract
Portions of a top compound semiconductor layer are recessed employing a gate electrode as an etch mask to form a source trench and a drain trench. A low temperature epitaxy process is employed to deposit a semiconductor material including at least one elemental semiconductor material in the source trench and the drain trench. Metallization is performed on physically exposed surfaces of the elemental semiconductor material portions in the source trench and the drain trench by depositing a metal and inducing interaction with the metal and the at least one elemental semiconductor material. A metal semiconductor alloy of the metal and the at least one elemental semiconductor material can be performed at a temperature lower than 600° C. to provide a high electron mobility transistor with a well-defined device profile and reliable metallization contacts.
-
Citations
11 Claims
-
1. A semiconductor structure comprising a high electron mobility transistor (HEMT), wherein said HEMT comprises:
-
a substrate comprising a stack, from bottom to top, of a substrate compound semiconductor layer and a top compound semiconductor layer; a gate electrode contacting a horizontal surface of a portion of said top compound semiconductor layer; a source region embedded in said substrate; and a drain region embedded in said substrate and laterally spaced from said source region, wherein said second portion is laterally spaced from said first portion by a width of said gate electrode, and wherein each of said source region and said drain region comprises at least one elemental semiconductor material. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
-
-
11-20. -20. (canceled)
Specification