MEMORY-NETWORK PROCESSOR WITH PROGRAMMABLE OPTIMIZATIONS

• US 20140351551A1
• Filed: 05/23/2014
• Published: 11/27/2014
• Est. Priority Date: 05/24/2013
• Status: Active Grant

• Current Assignee: Coherent Logix, Incorporated
• Original Assignee: Coherent Logix, Incorporated
• Inventors: Doerr, Michael B., Dobbs, Carl S., Solka, Michael B., Trocino, Michael R., Faulkner, Kenneth R., Bindloss, Keith M., Beardslee, John Mark, Gibson, David A., Arya, Sumeer
• Granted Patent: US 9,430,369 B2
• Time in Patent Office: Days
• US Class Current: 711/204
• CPC Class Codes: G06F 12/0215 with look ahead addressing means
• CPC Class Codes: G06F 9/3005 to perform operations for flow control
• CPC Class Codes: G06F 9/30083 Power or thermal control instructions
• CPC Class Codes: G06F 9/30145 Instruction analysis, e.g. decoding, instruction word fields
• CPC Class Codes: G06F 9/30181 Instruction operation extension or modification
• CPC Class Codes: G06F 9/3802 Instruction prefetching
• CPC Class Codes: G06F 9/3826 Bypassing or forwarding of data results, e.g. locally between pipeline stages or within a pipeline stage
• CPC Class Codes: G06F 9/3851 from multiple instruction streams, e.g. multistreaming
• CPC Class Codes: G06F 9/3853 of compound instructions
• CPC Class Codes: G06F 9/3867 using instruction pipelines
• CPC Class Codes: G06F 9/3885 using a plurality of independent parallel functional units
• CPC Class Codes: G06F 9/3895 for complex operations, e.g. multidimensional or interleaved address generators, macros
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

Various embodiments are disclosed of a multiprocessor system with processing elements optimized for high performance and low power dissipation and an associated method of programming the processing elements. Each processing element may comprise a fetch unit and a plurality of address generator units and a plurality of pipelined datapaths. The fetch unit may be configured to receive a multi-part instruction, wherein the multi-part instruction includes a plurality of fields. A first address generator unit may be configured to perform an arithmetic operation dependent upon a first field of the plurality of fields. A second address generator unit may be configured to generate at least one address of a plurality of addresses, wherein each address is dependent upon a respective field of the plurality of fields. A parallel assembly language may be used to control the plurality of address generator units and the plurality of pipelined datapaths.

Claims

1. An apparatus, comprising:

a fetch unit configured to receive a multi-part instruction, wherein the multi-part instruction includes a plurality of fields; and

a plurality of address generator units;

wherein a first address generator unit of the plurality of address generator units is configured to perform an arithmetic operation dependent upon a first field of the plurality of fields; and

wherein a second address generator unit is configured to generate at least one address of a plurality of addresses, wherein each address of the plurality of addresses is dependent upon a respective field of the plurality of fields.

2. The apparatus of claim 1, further comprising a store unit configured to store first data dependent upon a first address of the plurality of addresses.

3. The apparatus of claim 2, wherein the fetch unit is further configured to fetch second data dependent upon a second address of the plurality of addresses.

4. The apparatus of claim 1, wherein a third address generator unit is configured to generate at least another address of the plurality of addresses.

5. The apparatus of claim 1, wherein each field of a subset of the plurality of fields encodes an operation to be performed by a respective address generator unit of the plurality of address generator units.

6. A method for operating a processor, the method comprising:

receiving a multi-part instruction, wherein the multi-part instruction includes a plurality of fields;

performing an arithmetic operation dependent on a first field of the plurality of fields; and

generating a given address of a plurality of addresses dependent upon a respective field of the plurality of fields.

7. The method of claim 6, further comprising storing first data dependent upon a first address of the plurality of addresses.

8. The method of claim 7, further comprising fetching second data dependent upon a second address of the plurality of addresses.

9. The method of claim 6, wherein the processor includes a plurality of address generator units, and wherein performing the arithmetic operation comprises performing the arithmetic operation using at least one address generator unit of the plurality of address generator units.

10. The method of claim 9, wherein each field of a subset of the plurality of fields encodes an operation to be performed by a respective address generator unit of the plurality of address generators units.

11. A system, comprising:

a plurality of processors; and

a plurality of dynamically configurable communication elements;

wherein the plurality of processors and the plurality of dynamically configurable communication elements are coupled together in an interspersed arrangement;

wherein a given processor of the plurality of processors is configured to;

receive a multi-part instruction, wherein the multi-part instruction includes a plurality of fields;

perform an arithmetic operation dependent upon a given field of the plurality of fields; and

generate a plurality of addresses dependent upon a subset of the plurality of fields.

12. The system of claim 11, wherein each processor of the plurality of processors if further configured to store first data dependent upon a first address of the plurality of addresses.

13. The system of claim 12, wherein the given processor of the plurality of processors is further configured to fetch second data dependent upon a second address of the plurality of addresses.

14. The system of claim 11, wherein the given processor of the plurality of processors includes a plurality of address generator units.

15. The system of claim 14, wherein each field of a subset of the plurality of fields encodes an operation to be performed by a respective address generator unit of the plurality of address generator units.