SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF

• US 20140361352A1
• Filed: 06/06/2013
• Published: 12/11/2014
• Est. Priority Date: 06/06/2013
• Status: Active Grant

• Current Assignee: United Microelectronics Corporation
• Original Assignee: United Microelectronics Corporation
• Inventors: Hung, Ching-Wen, Huang, Chih-Sen, Tsao, Po-Chao, Tzou, Shih-Fang
• Granted Patent: US 9,006,804 B2
• Time in Patent Office: Days
• US Class Current: 257/288
• CPC Class Codes: H01L 21/28008 Making conductor-insulator-semiconductor electrodes
• CPC Class Codes: H01L 21/28079 the final conductor layer next to the insulator being a single metal, e.g. Ta, W, Mo, Al
• CPC Class Codes: H01L 21/28088 the final conductor layer next to the insulator being a composite, e.g. TiN
• CPC Class Codes: H01L 21/31111 by chemical means
• CPC Class Codes: H01L 21/31144 using masks
• CPC Class Codes: H01L 21/32053 of metal-silicide layers
• CPC Class Codes: H01L 21/76832 Multiple layers
• CPC Class Codes: H01L 21/76834 formation of thin insulating films on the sidewalls or on top of conductors H01L21/76831 takes precedence
• CPC Class Codes: H01L 21/76897 Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step self-aligned silicidation on field effect transistors H01L29/665
• CPC Class Codes: H01L 23/485 consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts H01L23/4821, H01L23/4822, H01L23/4824, H01L23/4825 take precedence; materials H01L23/532, bond pads H01L24/02, bump connectors H01L24/10
• CPC Class Codes: H01L 29/665 using self aligned silicidation, i.e. salicide formation of conductive layers comprising silicides H01L21/28518
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/6656 using multiple spacer layers, e.g. multiple sidewall spacers
• CPC Class Codes: H01L 29/78 with field effect produced by an insulated gate H01L29/7725, H01L29/775, H01L29/778 take precedence
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A method for fabricating a semiconductor device is provided herein and includes the following steps. First, a first interlayer dielectric is formed on a substrate. Then, a gate electrode is formed on the substrate, wherein a periphery of the gate electrode is surrounded by the first interlayer dielectric. Afterwards, a patterned mask layer is formed on the gate electrode, wherein a bottom surface of the patterned mask layer is leveled with a top surface of the first interlayer dielectric. A second interlayer dielectric is then formed to cover a top surface and each side surface of the patterned mask layer. Finally, a self-aligned contact structure is formed in the first interlayer dielectric and the second interlayer dielectric.

Claims

1. A method for fabricating a semiconductor device, comprising:

forming a first interlayer dielectric on a substrate;

forming a gate electrode on the substrate, wherein a periphery of the gate electrode is surrounded by the first interlayer dielectric;

forming a patterned mask layer on the gate electrode, wherein a bottom surface of the patterned mask layer is leveled with a top surface of the first interlayer dielectric;

forming a second interlayer dielectric to cover a top surface and sidewalls of the patterned mask layer; and

forming a self-aligned contact structure in the first interlayer dielectric and the second interlayer dielectric.

2. The method of claim 1, further comprising:

forming a dummy gate electrode on the substrate;

removing the dummy gate electrode to leave a trench;

forming a gate electrode in the trench;

depositing a metal layer to fill up the trench; and

removing a portion of the metal layer until the first interlayer dielectric is exposed.

3. The method of claim 2, further comprising:

forming a gate spacer on each sidewall of the dummy gate electrode;

conformally depositing an etch stop layer on each of the gate spacers; and

forming the self-aligned contact structure in the first interlayer dielectric and the second interlayer dielectric, wherein the self-aligned contact structure directly contacts the etch stop layer.

4. The method of claim 1, wherein the top surface of the first interlayer dielectric is substantially leveled with the top surface of the gate electrode before forming the patterned mask layer.

5. The method of claim 1, further comprising:

depositing a mask layer to directly cover a top surface of the gate electrode; and

etching the mask layer to form the patterned mask layer.

6. The method of claim 1, wherein a width of the patterned mask layer is substantially larger than a width of the gate electrode.

7. The method of claim 1, further comprising forming a spacer on each sidewall of the patterned mask layer before forming the self-aligned contact structure.

8. The method of claim 7, wherein each of the spacers has a stack structure comprising an oxide layer and a nitride layer from bottom to top.

9. The method of claim 1, wherein a step for forming the spacer comprises:

conformally depositing a dielectric layer on the patterned mask layer; and

etching the dielectric layer to expose the first interlayer dielectric.

10. The method of claim 1, wherein a step for forming the self-aligned contact structure comprises:

sequentially etching the second interlayer dielectric, the patterned mask layer and the first interlayer dielectric to form a contact hole, wherein the contact hole exposes a region of the substrate;

forming a silicide in the region; and

forming a metal layer to fill up the contact hole.

11. The method of claim 1, wherein the self-aligned contact structure directly contacts the patterned mask layer.

12. A semiconductor device, comprising:

a metal gate electrode, disposed on a substrate;

a first interlayer dielectric, surrounding a periphery of the metal gate electrode;

a patterned mask layer, disposed on the metal gate electrode, wherein a bottom surface of the patterned mask layer is leveled with a top surface of the first interlayer dielectric;

a second interlayer dielectric, covering a top surface and at least a sidewall of the patterned mask layer; and

a self-aligned contact structure disposed in the first interlayer dielectric and the second interlayer dielectric, and electrically connecting the substrate.

13. The semiconductor device of claim 12, wherein a top surface of the metal gate electrode is substantially leveled with the top surface of the first interlayer dielectric.

14. The semiconductor device of claim 12, wherein the first interlayer dielectric and the second interlayer dielectric comprise silicon oxide.

15. The semiconductor device of claim 12, wherein the patterned mask layer comprises silicon nitride, silicon carbon nitride, silicon oxynitride or silicon carbide.

16. The semiconductor device of claim 12, wherein a width of the patterned mask layer is substantially larger than a width of the metal gate electrode.

17. The semiconductor device of claim 12, further comprising a spacer disposed on sidewalls of the patterned mask layer.

18. The semiconductor device of claim 17, wherein each of the spacers comprises silicon nitride, silicon carbon nitride, silicon oxynitride or silicon carbide.

19. The semiconductor device of claim 17, wherein the patterned mask layer and each of the spacer cover the metal gate electrode completely.

20. The semiconductor device of claim 12, further comprising:

a gate spacer, disposed on sidewalls of the metal gate electrode; and

an etch stop layer, disposed between each of the gate spacers and the self-aligned contact structure.

21. The semiconductor device of claim 20, wherein each of the gate spacers and each of the etch stop layers comprise silicon nitride, silicon carbon nitride, silicon oxynitride or silicon carbide.