SYSTEM AND METHOD FOR BIT PROCESSING IN A CENTRAL NETWORK COMPONENT

• US 20140362893A1
• Filed: 06/10/2013
• Published: 12/11/2014
• Est. Priority Date: 06/10/2013
• Status: Active Application

• Current Assignee: NXP B.V. (NXP Semiconductors NV)
• Original Assignee: NXP B.V. (NXP Semiconductors NV)
• Inventors: Deb, Abhijit Kumar, Vermeulen, Hubertus Gerardus Hendrikus, Pandey, Sujan
• Granted Patent: US 10,284,247 B2
• Time in Patent Office: Days
• US Class Current: 375/219
• CPC Class Codes: H04B 1/3822 specially adapted for use in vehicles H04B1/3827 takes precedence
• CPC Class Codes: H04L 12/40013 Details regarding a bus controller

Abstract

A central network component, a FlexRay-compatible central network component, and a method for bit processing in a central network component are described. In one embodiment, a central network component for facilitating communication among communication nodes includes a bit oversampling module configured to oversample bits received from a first communication node of the communication nodes with an oversampling factor to generate oversampled bit streams, a time point selection module configured to select time points in the oversampled bit streams, where the time points correspond to inner samples of the oversampled bit streams with respect to the oversampling factor, and a bit outputting module configured to output the inner samples to a second communication node of the communication nodes between the time points. Other embodiments are also described.

Claims

1. A central network component for facilitating communication among communication nodes, the central network component comprising:

a bit oversampling module configured to oversample a plurality of bits received from a first communication node of the communication nodes with an oversampling factor to generate oversampled bit streams;

a time point selection module configured to select time points in the oversampled bit streams, wherein the time points correspond to inner samples of the oversampled bit streams with respect to the oversampling factor; and

a bit outputting module configured to output the inner samples to a second communication node of the communication nodes between the time points.

2. The central network component of claim 1, wherein the bit outputting module is further configured to output one of the inner samples out of the central network component between a corresponding time point of the time points and a subsequent time point of the time points.

3. The central network component of claim 1, wherein the bit outputting module is further configured to, from one of the time points, keep a corresponding one of the inner samples as the output bit of the central network component until a next time point.

4. The central network component of claim 1, wherein the time point selection module is further configured to:

increase a sample counter for each bit in one of the oversampled bit streams; and

select a time point in the one of the oversampled bit streams when the sample counter is around a half of the oversampling factor.

5. The central network component of claim 1, wherein the bit oversampling module is further configured to oversample a first received bit to generate a first oversampled bit stream and oversample a second received bit to generate a second oversampled bit stream, wherein the time point selection module is further configured to select a first time point that corresponds to an inner sample in the first oversampled bit stream and select a second time point that corresponds to an inner sample in the second oversampled bit stream, wherein the bit outputting module is further configured to output the inner sample in the first oversampled bit stream to the second communication node between the first time point and the second time point.

6. The central network component of claim 1, wherein the plurality of bits includes a bit pattern that is known to the central network component, and wherein the time point selection module is further configured to adjust a sample counter in response to the bit pattern.

7. The central network component of claim 1, wherein the time point selection module is further configured to select the time points in the oversampled bit streams such that time differences between adjacent time points are equivalent.

8. The central network component claim 1, further comprising a bit majority voting module configured to perform major voting to the oversampled bit streams.

9. The central network component of claim 8, wherein the bit majority voting module is further configured to perform the major voting to the oversampled bit streams using a slide window having odd number of samples.

10. The central network component of claim 1, wherein the central network component is used in an automobile system.

11. The central network component of claim 1, wherein the central network component is a FlexRay-compatible bus guardian.

12. A FlexRay-compatible central network component for facilitating communication among FlexRay-compatible communication nodes in an automobile system, the FlexRay-compatible central network component comprising:

a bit oversampling module configured to oversample a plurality of bits received from a first FlexRay-compatible communication node of the FlexRay-compatible communication nodes with an oversampling factor to generate oversampled bit streams;

a time point selection module configured to select time points in the oversampled bit streams, wherein the time points correspond to inner samples of the oversampled bit streams with respect to the oversampling factor; and

a bit outputting module configured to output the inner samples to a second FlexRay-compatible communication node of the FlexRay-compatible communication nodes between the time points.

13. The FlexRay-compatible central network component of claim 12, wherein the FlexRay-compatible central network component is a FlexRay-compatible bus guardian.

14. A method for bit processing in a central network component for facilitating communication among communication nodes, the method comprising:

oversampling a plurality of bits received at the central network component from a first communication node of the communication nodes with an oversampling factor to generate oversampled bit streams;

selecting time points in the oversampled bit streams, wherein the time points correspond to inner samples of the oversampled bit streams with respect to the oversampling factor; and

outputting the inner samples out of the central network component to a second communication node of the communication nodes between the time points.

15. The method of claim 14, wherein outputting the inner samples comprises outputting one of the inner samples out of the central network component between a corresponding time point of the time points and a subsequent time point of the time points.

16. The method of claim 14, wherein outputting the inner samples comprises from one of the time points, keeping a corresponding one of the inner samples as the output bit of the central network component until a next time point.

17. The method of claim 14, wherein selecting the time points in the oversampled bit streams comprises:

increasing a sample counter for each bit in one of the oversampled bit streams; and

selecting a time point in the one of the oversampled bit streams when the sample counter is around a half of the oversampling factor.

18. The method of claim 14, wherein the plurality of bits includes a bit pattern that is known to the central network component, and wherein the method further comprises adjusting a sample counter in response to the bit pattern.

19. The method of claim 14 further comprising performing major voting to the oversampled bit streams using a slide window having odd number of samples.

20. The method of claim 14, wherein the central network component is a FlexRay-compatible bus guardian.