METHOD OF TESTING SEMICONDUCTOR DEVICE

• US 20140363906A1
• Filed: 04/01/2014
• Published: 12/11/2014
• Est. Priority Date: 06/07/2013
• Status: Active Grant

• Current Assignee: Mitsubishi Electric Corporation
• Original Assignee: Mitsubishi Electric Corporation
• Inventors: OTSUKI, Eiko, YOSHIURA, Yasuhiro, SADAMATSU, Koji
• Granted Patent: US 9,401,314 B2
• Time in Patent Office: Days
• US Class Current: 438/17
• CPC Class Codes: G01R 31/129 of components or parts made of semiconducting materials; of LV components or parts G01R31/18 takes precedence
• CPC Class Codes: H01L 22/14 for electrical parameters, e.g. resistance, deep-levels, CV, diffusions by electrical means
• CPC Class Codes: H01L 29/0619 with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
• CPC Class Codes: H01L 29/063 Reduced surface field [RESURF] pn-junction structures
• CPC Class Codes: H01L 29/739 controlled by field-effect, e.g. bipolar static induction transistors [BSIT] unijunction transistors H01L29/705
• CPC Class Codes: H01L 29/861 Diodes

Abstract

A method of testing a semiconductor device having a substrate in and on which a cell structure and a termination structure are formed, the cell structure having a main current flowing therethrough, the termination structure surrounding the cell structure, the method includes a first test step of testing dielectric strength of the semiconductor device, a charge removal step of, after the first test step, removing charge from a top surface layer of the termination structure, the top surface layer being located on the substrate and formed of an insulating film or a semi-insulating film, and a second test step of, after the charge removal step, testing dielectric strength of the semiconductor device.

Claims

1. A method of testing a semiconductor device having a substrate in and on which a cell structure and a termination structure are formed, said cell structure having a main current flowing therethrough, said termination structure surrounding said cell structure, said method comprising:

a first test step of testing dielectric strength of said semiconductor device;

a charge removal step of, after said first test step, removing charge from a top surface layer of said termination structure, said top surface layer being located on said substrate and formed of an insulating film or a semi-insulating film; and

a second test step of, after said charge removal step, testing dielectric strength of said semiconductor device.

2. The method according to claim 1, wherein:

said termination structure has a channel stopper on a side thereof opposite that adjacent said cell structure, said channel stopper being formed in a top surface side of said substrate;

said cell structure includes a top surface electrode formed in contact with an adjacent side of said top surface layer;

said termination structure includes a peripheral electrode formed in contact with said channel stopper and in contact with a side of said top surface layer adjacent said channel stopper; and

said charge removal step includes bringing a first conductor formed at one end of a resistor device into contact with said top surface electrode and a second conductor formed at the other end of said resistor device into contact with said peripheral electrode.

10. The method according to claim 1, wherein said termination structure includes an FLR structure, a RESURF structure, or a VLD structure formed in a top surface side of said substrate.

11. The method according to claim 1, wherein:

said termination structure includes a plurality of FLRs formed in a top surface side of said substrate; and

said top surface layer is formed on and in contact with said plurality of FLRs.

12. The method according to claim 1, wherein said semiconductor device is a diode, an IGBT, or a MOSFET.

3. A method of testing a semiconductor device having a substrate in and on which a cell structure and a termination structure are formed, said cell structure having a main current flowing therethrough, said termination structure surrounding said cell structure and having on a top surface thereof a top surface layer formed of an insulating film or a semi-insulating film, said method comprising:

a charge removal step of removing charge from said top surface layer; and

a test step of, after said charge removal step, testing dielectric strength of said semiconductor device.

4. The method according to claim 3, wherein said charge removal step includes bringing a conductor formed at one end of a grounding device into contact with said top surface layer, with the other end of said grounding device being grounded.

5. The method according to claim 4, wherein said conductor has a needle-like shape.

6. The method according to claim 4, wherein said conductor has a strip-like shape.

7. The method according to claim 4, wherein said conductor is a conductive ribbon.

8. A method of testing a semiconductor device having a substrate in and on which a cell structure and a termination structure are formed, said cell structure having a main current flowing therethrough, said termination structure surrounding said cell structure and having on a top surface thereof a top surface layer which is formed of an insulating film or a semi-insulating film and which is covered with a sealing material, said method comprising:

a sealing material removal step of removing said sealing material to expose said top surface layer; and

a charge removal step of, after said sealing material removal step, removing charge from said top surface layer.

9. The method according to claim 8, wherein said charge removal step includes bringing a first conductor formed at one end of a voltage apply device into contact with said top surface layer and a second conductor formed at the other end of said voltage apply device into contact with a bottom surface of said semiconductor device, and applying a voltage between said first and second conductors so as to eliminate charge on said top surface layer.