Independent Management of Data and Parity Logical Block Addresses

• US 20140365821A1
• Filed: 08/26/2014
• Published: 12/11/2014
• Est. Priority Date: 03/21/2011
• Status: Active Grant

• Current Assignee: Apple Inc.
• Original Assignee: Apple Inc.
• Inventors: Golov, Oren, Sommer, Naftali, Meir, Avraham Poza, Neerman, Moshe
• Granted Patent: US 9,170,885 B2
• Time in Patent Office: Days
• US Class Current: 714/6.24
• CPC Class Codes: G06F 11/10 Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
• CPC Class Codes: G06F 11/1068 in sector programmable memories, e.g. flash disk G06F11/1072 takes precedence
• CPC Class Codes: G06F 11/108 Parity data distribution in semiconductor storages, e.g. in SSD
• CPC Class Codes: G06F 11/1096 Parity calculation or recalculation after configuration or reconfiguration of the system
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 12/06 Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication G06F12/08 takes precedence
• CPC Class Codes: G06F 2211/1059 Parity-single bit-RAID5, i.e. RAID 5 implementations
• CPC Class Codes: G06F 2212/7205 Cleaning, compaction, garbage collection, erase control
• CPC Class Codes: G06F 3/0616 in relation to life time, e.g. increasing Mean Time Between Failures [MTBF]
• CPC Class Codes: G06F 3/064 Management of blocks
• CPC Class Codes: G06F 3/0688 Non-volatile semiconductor memory arrays

Abstract

A data storage method includes identifying, in a set of data items associated with respective logical addresses for storage in a memory, a first subset of the logical addresses associated with the data items containing application data, and a second subset of the logical addresses associated with the data items containing parity information that has been calculated over the application data. The data items associated with the first identified subset are stored in one or more first physical memory areas of the memory, and the data items associated with the second identified subset are stored in one or more second physical memory areas of the memory, different from the first physical memory areas. A memory management task is performed independently in the first physical memory areas and in the second physical memory areas.

Claims

1. An apparatus, comprising:

an interface configured to receive at least application data for storage in a memory; and

a processor configured to;

identify, in a set of data items associated with respective logical addresses for storage in the memory, a first subset of the logical addresses associated with the data items that include the application data;

identify a second subset of the logical addresses with the data items containing parity information that has been calculated over the application data;

store data items associated with the first subset in first physical areas of the memory;

store data items associated with the second identified subset in second physical memory areas of the memory, wherein the second physical areas of the memory are different from the first physical areas of the memory; and

perform a memory management task independently in the first physical areas of the memory and in the second physical areas of the memory.

2. The apparatus of claim 1, wherein the interface is further configured to:

accept the set of data items and the respective logical addresses from the host; and

provide the data items and the respective logical addresses to the processor.

3. The apparatus of claim 1, wherein the processor is further configured to assign a first over-provisioning overhead to the first physical areas of memory, and assign a second over-provisioning overhead to the second physical areas of memory, wherein the second over-provisioning overhead is different from the first over-provisioning overhead.

4. The apparatus of claim 1, wherein to perform the memory management task, the processor is further configured to perform compaction in the first physical areas of the memory, and to perform compaction in the second physical areas of the memory independent of an operation performed in the first physical areas of the memory.

5. The apparatus of claim 1, wherein to perform the memory management task, the processor is further configured to perform static wear leveling in the first physical areas of the memory, and perform static wear leveling in the second physical areas of the memory independent an operation performed in the first physical areas of the memory.

6. The apparatus of claim 1, wherein the processor is further configured to identify one or more parameters of a redundant storage scheme, and to identify the first subset and the second subset dependent upon the one or more parameters.

7. A method, comprising:

receiving, by a controller, a plurality of data items and a respective plurality of logical addresses, wherein the plurality of data items includes a plurality of application data items and a plurality of parity data items;

identifying, by the controller, a first subset of the plurality of logical addresses and a second subset of the plurality of logical addresses dependent upon one or more parameters, wherein each logical address of the first subset of the plurality of logical addresses corresponds to a respective application data items of the plurality of application data items, and wherein each logical address of the second subset of the plurality of logical addresses corresponds to a respective parity data item of the plurality of parity data items;

storing, by the controller, each application data item of the plurality of application data items in a first portion of a memory dependent upon the first subset of the plurality of logical addresses; and

storing, by the controller, each parity data item of the plurality of data items in a second portion of the memory dependent upon the second subset of the plurality of logical addresses.

8. The method of claim 7, further comprising receiving, by the controller, at least one command, wherein the at least one command includes the one or more parameters.

9. The method of claim 7, wherein receiving, by the controller, the plurality of data items and the respective plurality of logical addresses, comprises receiving, by the controller, via a first interface, the plurality of data items and the respective plurality of logical addresses, and further comprising receiving, by the controller, via a second interface, the one or more parameters.

10. The method of claim 7, further comprising extracting the one or more parameters from at least one data structure stored in the memory.

11. The method of claim 7, wherein identifying, by the controller, the first subset of the plurality of logical addresses and the second subset of the plurality of logical addresses dependent upon one or more parameters comprises analyzing a distribution of the plurality of logical addresses.

12. The method of claim 7, wherein the one or more parameters are dependent upon a frequency of write commands.

13. The method of claim 10, further comprising sending the extracted one or more parameters to an external agent.

14. An apparatus, comprising:

a memory; and

a processor configured to;

receive a plurality of data items and a respective plurality of logical addresses, wherein the plurality of data items includes a plurality of application data items and a plurality of parity data items;

identify a first subset of the plurality of logical addresses and a second subset of the plurality of logical addresses dependent upon one or more parameters, wherein each logical address of the first subset of the plurality of logical addresses corresponds to a respective application data items of the plurality of application data items, and wherein each logical address of the second subset of the plurality of logical addresses corresponds to a respective parity data item of the plurality of parity data items;

store each application data item of the plurality of application data items in a first portion of the memory dependent upon the first subset of the plurality of logical addresses; and

store each parity data item of the plurality of data items in a second portion of the memory dependent upon the second subset of the plurality of logical addresses.

15. The apparatus of claim 14, wherein the processor is further configured to receive at least one command, wherein the at least one command includes the one or more parameters.

16. The apparatus of claim 14, wherein to receive the plurality of data items and the respective plurality of logical addresses, the processor is further configured to receive the plurality of data items and the respective plurality of logical addresses via a first interface, and wherein the processor is further configured to receive the one or more parameters via a second interface.

17. The apparatus of claim 14, wherein the processor is further configured to extract the one or more parameters from at least one data structure stored in the memory.

18. The apparatus of claim 14, wherein to identify the first subset of the plurality of logical addresses and the second subset of the plurality of logical addresses dependent upon one or more parameters the processor is further configured to analyzing a distribution of the plurality of logical addresses.

19. The apparatus of claim 14, wherein the one or more parameters are dependent upon a frequency of write commands.

20. The apparatus of claim 14, wherein the processor is further configured to send the extracted one or more parameters to an external agent.