SEMICONDUCTOR DEVICE, METHOD FOR FABRICATING THE SAME, AND MEMORY SYSTEM INCLUDING THE SEMICONDUCTOR DEVICE

• US 20140369115A1
• Filed: 01/15/2014
• Published: 12/18/2014
• Est. Priority Date: 06/13/2013
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: WON, Seok-Jun, YI, Ji-Hye, KIM, Kook-Tae, KIM, Young-Tak, SON, Ho-Sung, LEE, Chul-Woong
• Granted Patent: US 9,312,376 B2
• Time in Patent Office: Days
• US Class Current: 365/182
• CPC Class Codes: H01L 29/41783 Raised source or drain electrodes self aligned with the gate
• CPC Class Codes: H01L 29/4966 the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2 H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H01L 29/4983 with a lateral structure, e.g. a Polysilicon gate with a lateral doping variation or with a lateral composition variation or characterised by the sidewalls being composed of conductive, resistive or dielectric material
• CPC Class Codes: H01L 29/518 the insulating material containing nitrogen, e.g. nitride, oxynitride, nitrogen-doped material
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/6656 using multiple spacer layers, e.g. multiple sidewall spacers
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/78 with field effect produced by an insulated gate H01L29/7725, H01L29/775, H01L29/778 take precedence
• CPC Class Codes: H01L 29/7848 the means being located in the source/drain region, e.g. SiGe source and drain
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/7851 with the body tied to the substrate

Abstract

Semiconductor device, method for fabricating the same and electronic devices including the semiconductor device are provided. The semiconductor device comprises an interlayer insulating layer formed on a substrate and including a trench, a gate electrode formed in the trench, a first gate spacer formed on a side wall of the gate electrode to have an L shape, a second gate spacer formed on the first gate spacer to have an L shape and having a dielectric constant lower than that of silicon nitride, and a third spacer formed on the second gate spacer.

Claims

1. A semiconductor device, comprising:

an interlayer insulating layer formed on a substrate and including a trench;

a gate electrode formed in the trench;

a first gate spacer formed on a side wall of the gate electrode to have an L shape;

a second gate spacer formed on the first gate spacer to have an L shape and having a dielectric constant lower than the dielectric constant of silicon nitride; and

a third spacer formed on the second gate spacer.

2. The semiconductor device of claim 1, wherein the second gate spacer has a dielectric constant which is higher than that of silicon oxide.

3. The semiconductor device of claim 2, wherein the second gate spacer includes SiOCN or SiOC.

4. The semiconductor device of claim 3, wherein the dielectric constant of the second gate spacer has a value between 4 and 6.

5. The semiconductor device of claim 1, wherein the first gate spacer and the third gate spacer include silicon nitride.

6. The semiconductor device of claim 1, wherein a top surface of the interlayer insulating layer and a top surface of the gate electrode are disposed on the same plane.

7. The semiconductor device of claim 6, further comprising:

a gate dielectric film formed between the gate electrode and the substrate,

wherein the gate dielectric film is formed along a side wall and a bottom surface of the trench.

8. The semiconductor device of claim 7, wherein the first gate spacer is formed to contact with the gate dielectric film.

9. The semiconductor device of claim 6, further comprising:

a gate dielectric film which is formed between the gate electrode and the substrate,

wherein the gate dielectric film is formed on a bottom surface of the trench.

10. The semiconductor device of claim 9, wherein the first gate spacer is formed to contact with the gate dielectric film and the gate electrode.

11. The semiconductor device of claim 1, further comprising:

an elevated source/drain formed at both sides of the gate electrode.

12. A semiconductor device, comprising:

an interlayer insulating layer formed on a substrate and including a trench;

a gate electrode formed in the trench, a top surface of the gate electrode being disposed on the same plane as a top surface of the interlayer insulating layer;

a first gate spacer formed on a side wall of the gate electrode to have an L shape and including SiOCN; and

a second gate spacer formed on the first gate spacer and including silicon nitride.

13. The semiconductor device of claim 12, further comprising a third spacer formed between the gate electrode and the first gate spacer to have an L shape,

wherein the first spacer is formed on the third spacer.

14. The semiconductor device of claim 13, wherein the third spacer includes silicon nitride.

15. The semiconductor device of claim 12, wherein a dielectric constant of the first gate spacer has a value between 4 and 6.

16. A memory card including the semiconductor device of claim 12 comprising:

a memory including the semiconductor device; and

a memory controller controlling data exchange between the memory and an outside host.

17. An information processing system including the semiconductor device of claim 12 comprising:

a system bus;

a memory system including the semiconductor device of claim 12 and electrically connected to the system bus;

a modem electrically connected to the system bus;

a central processing unit electrically connected to the system bus;

a random access memory electrically connected to the system bus; and

a user interface electrically connected to a system bus.

18. An electronic device including the semiconductor device of claim 12 comprising:

a controller configured to process commands to operate the electronic device;

a memory including the semiconductor device of claim 12 and storing the commands processed by the controller;

an input/output device for inputting and outputting information; and

a wireless interface with which exchanging data through a wireless data network.

19-21. -21. (canceled)