SUPPLY VOLTAGE GENERATING CIRCUIT

• US 20140375369A1
• Filed: 09/09/2014
• Published: 12/25/2014
• Est. Priority Date: 03/27/2007
• Status: Active Grant

• Current Assignee: Longitude Licensing Limited (Vector Capital Corporation)
• Original Assignee: PS4 Luxco S.a.r.l.
• Inventors: HAYASHI, Koichiro, TANAKA, Hitoshi
• Granted Patent: US 9,207,701 B2
• Time in Patent Office: Days
• US Class Current: 327/306
• CPC Class Codes: G05F 1/62 using bucking or boosting dc sources
• CPC Class Codes: G05F 3/02 Regulating voltage or current
• CPC Class Codes: G11C 11/4074 Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits
• CPC Class Codes: G11C 5/145 Applications of charge pumps; Boosted voltage circuits; Clamp circuits therefor G11C5/141 takes precedence
• CPC Class Codes: H02M 3/07 using capacitors charged and discharged alternately by semiconductor devices with control electrode , e.g. charge pumps

Abstract

A supply voltage generating circuit that enables a reduction in chip area includes: a booster for outputting a boosted voltage upon generating the boosted voltage by charge pumping of a capacitor element; a power-supply step-down unit for stepping down voltage of an external power supply to a voltage within a breakdown-voltage range of the capacitor element, and applying the stepped-down voltage to the power supply of the booster; and a switch element for switching between application of the external power supply to the power supply of the booster directly or via the power-supply step-down unit. The booster comprises multiple stages of booster circuits. The thicknesses of gate oxide films of capacitor elements constituted by MOS transistors included in respective ones of the booster circuits are the same and are made smaller than the thickness of a gate oxide film of a MOS transistor included in a load circuit having the output of the booster at its power supply.

Claims

1. A method for generating a supply voltage, comprising:

selecting one of a first input node supplied with a first power supply voltage and a second input nodes supplied with a second power supply voltage that is different from the first power supply voltage,

coupling a selected one of the first and second input nodes to an output node so that a boosted voltage at an output terminal takes a first level when the first input node is coupled to the output node and a second level when the second input node is coupled to the output node,

wherein the boosted voltage, which is greater than a voltage at the selected one of the first and second input nodes, is generated by a voltage booster circuit including first and second transistors and a capacitor, the first transistor being provided between the input terminal and one end of the capacitor, the second transistor being provided between the one end of the capacitor and the output terminal.

2. The method for generating a supply voltage as claimed in claim 1, wherein the first transistor is configured to supply the one end of the capacitor with the voltage at the selected one of the first and second input nodes, the capacitor being configured to be supplied with an additional voltage at the other end thereof to boost the voltage at the one end of the capacitor up to the boosted voltage, the second transistor being configured to supply the output terminal with the boosted voltage.

3. The method for generating a supply voltage as claimed in claim 1, wherein each of the first and second transistors is N-type.

4. The method for generating a supply voltage as claimed in claim 2, wherein the first transistor takes an ON-state when the second transistor takes an OFF-state and the first transistor takes an OFF-state when the second transistor takes an ON-state.

5. The method for generating a supply voltage as claimed in claim 2, wherein the boosted voltage takes approximately a sum of the voltage at the selected one of the first and second input nodes and the additional voltage.

6. The method for generating a supply voltage as claimed in claim 1, wherein the output node supplies the boosted voltage to a circuit for driving a word line.

7. The method for generating a supply voltage as claimed in claim 6, wherein thicknesses of gate oxide films of the first and second transistors are less than thicknesses of gate oxide film of transistors in the circuit for driving a word line.

8. The method for generating a supply voltage as claimed in claim 1, wherein the voltage booster circuit includes multiple booster circuits.

9. The method for generating a supply voltage as claimed in claim 8, wherein the voltage booster circuit includes a switch element to change a number of stages of the multiple booster circuits.

10. The method for generating a supply voltage as claimed in claim 1, further comprising decreasing an external voltage to become one of the first power supply voltage and the second power supply voltage.