MANUFACTURING METHOD OF LOW TEMPERATURE POLY-SILICON TFT ARRAY SUBSTRATE

  • US 20150011055A1
  • Filed: 09/24/2014
  • Published: 01/08/2015
  • Est. Priority Date: 05/27/2011
  • Status: Active Grant
First Claim
Patent Images

1. A manufacturing method of a low temperature poly-silicon thin film transistor (LTPS-TFT) array substrate, comprising:

  • sequentially forming a poly-silicon layer and a data-line-metal layer on a base substrate, and performing a patterning process by using a mask to simultaneously form an active layer and source and drain electrodes, the active layer being provided on the base substrate and the source and drain electrodes being provided on the active layer,wherein the method comprises;

    Step 1 of depositing a gate-metal-layer on the base substrate, and performing a patterning process by using a first mask to form a gate electrode;

    Step 2 of depositing a gate insulating layer on the base substrate after Step 1, the gate insulating layer covering the base substrate and the gate electrode;

    Step 3 of sequentially forming the poly-silicon layer and the data-line-metal layer on the base substrate after Step 2, and performing the patterning process by using a third mask to simultaneously form the active layer and the source and drain electrodes, the active layer being provided on the gate insulating layer and corresponding to the gate electrode; and

    Step 4 of depositing a transparent conductive layer on the base substrate after Step 3, and performing a patterning process by using a fourth mask to form a pixel electrode, the pixel electrode being provided on the source and drain electrodes and the gate insulating layer.

View all claims
    ×
    ×

    Thank you for your feedback

    ×
    ×