CLOSED LOOP DYNAMIC VOLTAGE AND FREQUENCY SCALING

• US 20150022272A1
• Filed: 07/22/2013
• Published: 01/22/2015
• Est. Priority Date: 07/22/2013
• Status: Active Grant

• Current Assignee: NVIDIA Corporation
• Original Assignee: NVIDIA Corporation
• Inventors: RAJA, Tezaswi, BOLLAPALLI, Kalyana, FELIX, Stephen, BOND, Jeffery, MEHTA, Vikram
• Granted Patent: US 9,766,649 B2
• Time in Patent Office: Days
• US Class Current: 331/17
• CPC Class Codes: G06F 1/08 Clock generators with changeable or programmable clock frequency
• CPC Class Codes: G06F 1/324 by lowering clock frequency
• CPC Class Codes: G06F 1/3296 by lowering the supply or operating voltage
• CPC Class Codes: H03L 1/00 Stabilisation of generator output against variations of physical values, e.g. power supply
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A system is based on an IC. A first component of the IC generates a signal that clocks the IC at a target operating frequency. A period corresponding to the target clock frequency exceeds a duration of a longest critical path associated with the IC. The first component and synchronous logic of the IC clocked therewith, each functions with the core supply voltage, which may be supplied to each via the same power supply rail. A second IC component detects errors that relate to an operation of the IC at the target clock frequency and determines a level for adjusting the core supply voltage. The Vdd adjustment ameliorates the frequency error. The voltage determination uses closed loop dynamic voltage and frequency scaling.

Claims

1. A system that is disposed on an integrated circuit (IC), which functions with a core supply voltage, the system comprising:

a first component operable to generate a clock signal for clocking the IC at a target frequency for operation, wherein a period that corresponds to the target operation clock frequency exceeds a duration of a longest critical path associated with the IC and wherein (a) the first component, and (b) a synchronous logic component of the IC clocked therewith, each functions with the core supply voltage, which is supplied to the first component and the synchronous logic component from the same power supply rail; and

a second component operable to detect frequency related errors that relate to an operation of the IC at the target operation clock frequency and for determining a level for adjusting the core supply voltage wherein the core supply voltage adjustment ameliorates the frequency related errors, wherein the voltage determination comprises closed loop dynamic voltage and frequency scaling.

2. The system as recited in claim 1 wherein the first component comprises a digitally parameterizable voltage controlled oscillator (DVCO) that, based on a determined level for adjusting the core supply voltage, is operable to output the clock signal.

3. The system as recited in claim 2 wherein the second component:

controls the DVCO, based on the determined level for adjusting the core supply voltage; and

outputs a signal that corresponds to the determined level for adjusting the core supply voltage.

4. The system as recited in claim 2 wherein an entity controls or regulates the core supply voltage based on the output signal, which corresponds to the determined level for adjusting the core supply voltage.

5. The system as recited in claim 4 wherein the core supply voltage control entity comprises a component that is independent of the IC.

6. The system as recited in claim 4 wherein the core supply voltage control entity comprises a power management IC (PMIC) component.

7. The system as recited in claim 4 wherein the second component provides the output signal, which corresponds to the determined level for adjusting the core supply voltage, to the core supply voltage control or regulation entity.

8. The system as recited in claim 2 wherein the frequency related errors comprise a deviation of an output frequency of the DVCO from the target operation clock frequency.

9. The system as recited in claim 2 wherein the second component comprises a cycle-error integrator, which detects the frequency related errors that relate to an operation of the IC at the target operation clock frequency.

10. The system as recited in claim 2 wherein the second component comprises a register, which stores a value that relates to one or more of:

the target clock operation frequency;

a parameter that relates to tuning the second component;

or

a parameter that relates to a gain, which is achieved in the second component.

11. A method for controlling a core supply voltage of an integrated circuit (IC), the method comprising:

generating a clock signal for clocking the IC at a target frequency for operation, wherein a period that corresponds to the target operation clock frequency exceeds a duration of a longest critical path associated with the IC and wherein (a) the first component, and (b) a synchronous logic component of the IC clocked therewith, each functions with the core supply voltage;

detecting frequency related errors that relate to an operation of the IC at the target operation clock frequency; and

determining a level for adjusting the core supply voltage wherein the core supply voltage adjustment ameliorates the frequency related error, wherein the determining comprises scaling using closed loop dynamic voltage and frequency scaling.

12. The method as recited in claim 11 wherein the clock generating comprises a dynamic voltage controlled oscillation (DVCO) that, based on the determined level for adjusting the core supply voltage, outputs the clock signal.

13. The method as recited in claim 12 wherein the determining comprises:

controlling the DVCO, based on the determined level for adjusting the core supply voltage; and

outputting a signal that corresponds to the determined level for adjusting the core supply voltage.

14. The method as recited in claim 12 wherein the determining functions with an entity that controls or regulates the core supply voltage based on the output signal, which corresponds to the determined level for adjusting the core supply voltage.

15. The method as recited in claim 14 wherein the determining entity comprises a component that is independent of the IC.

16. The method as recited in claim 14 wherein the entity comprises a power management IC (PMIC) component.

17. The method as recited in claim 14 further comprising providing an output signal, which corresponds to a determined level for adjusting the core supply voltage, to the core supply voltage control or regulation entity.

18. The method as recited in claim 12 wherein the frequency related errors comprise a deviation of an output frequency of the DVCO from the target operation clock frequency.

19. The method as recited in claim 12 wherein the detection of the errors, which relate to an operation of the IC at the target operation clock frequency, comprises cycle-error integration.

20. The method as recited in claim 12 wherein one or more of the detecting or the determining comprises storing a value that relates to one or more of:

the target clock operation frequency;

a parameter that relates to tuning the determination of the level for adjusting the core supply voltage;

or

a parameter that relates to a gain, which is achieved in the determination of the level for adjusting the core supply voltage.

21. A circuit, comprising:

means for supplying a core supply voltage to a plurality of components of an integrated circuit (IC) device;

means for generating a clock signal for clocking the IC at a target frequency for operation, wherein a period that corresponds to the target operation clock frequency exceeds a duration of a longest critical path associated with the IC, wherein (a) the first component, and (b) a synchronous logic component of the IC clocked therewith, each functions with the core supply voltage and wherein the plurality of components supplied with the core supply voltage by the voltage supplying means comprises the first component and the synchronous logic component clocked therewith;

means for detecting frequency related errors that relate to an operation of the IC at the target operation clock frequency; and

means for determining a level for adjusting the core supply voltage wherein the core supply voltage adjustment ameliorates the frequency related error, wherein the voltage determination means comprises means for closed loop dynamic voltage and frequency scaling.

22. An integrated circuit (IC) device that functions with a core control voltage, the IC comprising:

a semiconductor die; and

an array of active devices that are disposed in the semiconductor die, which are configured or programmed to function as system that comprises;

a first component for generating a clock signal for clocking the IC at a target frequency for operation, wherein a period that corresponds to the target operation clock frequency exceeds a duration of a critical path function or operation of the IC and wherein the clock generation component functions with the core supply voltage; and

a second component for detecting frequency related errors that relate to an operation of the IC at the target operation clock frequency and for determining a level for adjusting the core supply voltage wherein the core supply voltage adjustment ameliorates the frequency related error, wherein the voltage determination comprises closed loop dynamic voltage and frequency scaling.