METHOD AND APPARATUS FOR SELECTING A MEMORY BLOCK FOR WRITING DATA, BASED ON A PREDICTED FREQUENCY OF UPDATING THE DATA

• US 20150026387A1
• Filed: 07/18/2013
• Published: 01/22/2015
• Est. Priority Date: 07/22/2009
• Status: Active Grant

• Current Assignee: Marvell Asia Pte Limited (Marvell Technology Group Limited)
• Original Assignee: Joseph Sheredy, Lau Nguyen
• Inventors: Sheredy, Joseph, Nguyen, Lau
• Granted Patent: US 9,244,834 B2
• Time in Patent Office: Days
• US Class Current: 711/103
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 2212/7211 Wear leveling
• CPC Class Codes: G06F 3/0616 in relation to life time, e.g. increasing Mean Time Between Failures [MTBF]
• CPC Class Codes: G06F 3/064 Management of blocks
• CPC Class Codes: G06F 3/0679 Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 11/5635 Erasing circuits
• CPC Class Codes: G11C 16/16 for erasing blocks, e.g. arrays, words, groups
• CPC Class Codes: G11C 16/349 Arrangements for evaluating degradation, retention or wearout, e.g. by counting erase cycles
• CPC Class Codes: G11C 16/3495 Circuits or methods to detect or delay wearout of nonvolatile EPROM or EEPROM memory devices, e.g. by counting numbers of erase or reprogram cycles, by using multiple memory areas serially or cyclically
• CPC Class Codes: G11C 2211/5641 Multilevel memory having cells with different number of storage levels

Abstract

Some of the embodiments of the present disclosure provide a method for programming a flash memory having a plurality of memory blocks, wherein each memory block of the plurality of memory blocks is either a single-level cell (SLC) memory block or a multi-level cell (MLC) memory block, the method comprising assigning a weighting factor to each memory block of the plurality of memory blocks based on whether the memory block is an SLC memory block or an MLC memory block, tracking a number of write-erase cycles for each memory block, and selecting one or more memory blocks for writing data based at least in part on the weighting factor and the tracked number of write-erase cycles of each memory block of the plurality of memory blocks. Other embodiments are also described and claimed.

Claims

1. A method for storing data in a memory module comprising (i) a single-level cell memory block and (ii) a multi-level cell memory block, the method comprising:

prior to storing the data in the memory module, predicting a frequency with which the data is to be updated while being stored in the memory module;

based on the predicted frequency with which the data is to be updated while being stored in the memory module, selecting the single-level cell memory block or the multi-level cell memory block of the memory module; and

storing the data in the selected one of the single-level cell memory block or the multi-level cell memory block of the memory module.

2. The method of claim 1, wherein predicting the frequency with which the data is to be updated while being stored in the memory module further comprises:

based on information with respect to the data available within an operating system, predicting, by the operating system, the frequency with which the data is to be updated while being stored in the memory module.

3. The method of claim 1, wherein predicting the frequency with which the data is to be updated while being stored in the memory module further comprises:

based on a type of the data, predicting the frequency with which the data is to be updated while being stored in the memory module.

4. The method of claim 1, wherein predicting the frequency with which the data is to be updated while being stored in the memory module further comprises:

based on a frequency with which the data was previously updated, predicting the frequency with which the data is to be updated while being stored in the memory module.

5. The method of claim 1, wherein selecting the single-level cell memory block or the multi-level cell memory block of the memory module further comprises:

in response to the predicted frequency with which the data is to be updated while being stored in the memory module being greater than a predetermined threshold, selecting the single-level cell memory block; and

in response to the predicted frequency with which the data is to be updated while being stored in the memory module being smaller than the predetermined threshold, selecting the multi-level cell memory block.

6. The method of claim 5, wherein the single-level cell memory block comprises a plurality of single-level memory cells.

7. The method of claim 5, wherein the multi-level cell memory block comprises a plurality of multi-level memory cells.

8. The method of claim 1, wherein selecting the single-level cell memory block or the multi-level cell memory block of the memory module further comprises:

based on the predicted frequency with which the data is to be updated while being stored in the memory module, categorizing the data as one of a frequently updated data or an infrequently updated data; and

in response to categorizing the data as one of the frequently updated data or the infrequently updated data, selecting the single-level cell memory block or the multi-level cell memory block of the memory module.

9. The method of claim 8, wherein the single-level cell memory block comprises a plurality of single-level memory cells, wherein the multi-level cell memory block comprises a plurality of multi-level memory cells, and wherein selecting the single-level cell memory block or the multi-level cell memory block of the memory module further comprises:

in response to (i) the data being categorized as the frequently updated data and (ii) the single-level cell memory block comprising the plurality of single-level memory cells, selecting the single-level cell memory block; and

in response to (i) the data being categorized as the infrequently updated data and (ii) the multi-level cell memory block comprising the plurality of multi-level memory cells, selecting the multi-level cell memory block.

10. A system for storing data in a memory module, the system comprising:

the memory module comprising (i) a single-level cell memory block and (ii) a multi-level cell memory block; and

a selection module configured to

prior to storing the data in the memory module, predict a frequency with which the data is to be updated while being stored in the memory module, and

based on the predicted frequency with which the data is to be updated while being stored in the memory module, select the single-level cell memory block or the multi-level cell memory block of the memory module,

wherein the data is stored in the selected one of the single-level cell memory block or the multi-level cell memory block of the memory module.

11. The system of claim 10, wherein the selection module is configured to predict the frequency with which the data is to be updated while being stored in the memory module by:

based on information with respect to the data available within an operating system, predicting the frequency with which the data is to be updated while being stored in the memory module.

12. The system of claim 10, wherein the selection module is configured to predict the frequency with which the data is to be updated while being stored in the memory module by:

based on a type of the data, predicting the frequency with which the data is to be updated while being stored in the memory module.

13. The system of claim 10, wherein the selection module is configured to predict the frequency with which the data is to be updated while being stored in the memory module by:

based on a frequency with which the data was previously updated, predicting the frequency with which the data is to be updated while being stored in the memory module.

14. The system of claim 10, wherein the selection module is configured to select the single-level cell memory block or the multi-level cell memory block of the memory module by:

in response to the predicted frequency with which the data is to be updated while being stored in the memory module being greater than a predetermined threshold, selecting the single-level cell memory block; and

in response to the predicted frequency with which the data is to be updated while being stored in the memory module being smaller than the predetermined threshold, selecting the multi-level cell memory block.

15. The system of claim 14, wherein the single-level cell memory block comprises a plurality of single-level memory cells.

16. The system of claim 14, wherein the multi-level cell memory block comprises a plurality of multi-level memory cells.

17. The system of claim 10, wherein the selection module is configured to select one of the single-level cell memory block or the multi-level cell memory block of the memory module by:

based on the predicted frequency with which the data is to be updated while being stored in the memory module, categorizing the data as one of a frequently updated data or an infrequently updated data; and

in response to categorizing the data as one of the frequently updated data or the infrequently updated data, selecting the single-level cell memory block or the multi-level cell memory block of the memory module.

18. The system of claim 17, wherein the single-level cell memory block comprises a plurality of single-level memory cells, wherein the multi-level cell memory block comprises a plurality of multi-level memory cells, and wherein the selection module is further configured to select the single-level cell memory block or the multi-level cell memory block of the memory module by:

in response to (i) the data being categorized as the frequently updated data and (ii) the single-level cell memory block comprising the plurality of single-level memory cells, selecting the single-level cell memory block; and

in response to (i) the data being categorized as the infrequently updated data and (ii) the multi-level cell memory block comprising the plurality of multi-level memory cells, selecting the multi-level cell memory block.