Circuit and System of Using Junction Diode of MOS as Program Selector for Programmable Resistive Devices

• US 20150029777A1
• Filed: 09/22/2014
• Published: 01/29/2015
• Est. Priority Date: 08/20/2010
• Status: Active Grant

• Current Assignee: Attopsemi Technology Co., Ltd.
• Original Assignee: Shine C. Chung
• Inventors: Chung, Shine C.
• Granted Patent: US 9,236,141 B2
• Time in Patent Office: Days
• US Class Current: 365/96
• CPC Class Codes: G11C 11/1659 Cell access
• CPC Class Codes: G11C 11/1675 Writing or programming circuits or methods
• CPC Class Codes: G11C 13/0002 using resistive RAM [RRAM] elements
• CPC Class Codes: G11C 13/0004 comprising amorphous/crystalline phase transition cells
• CPC Class Codes: G11C 13/0007 comprising metal oxide memory material, e.g. perovskites
• CPC Class Codes: G11C 13/0011 comprising conductive bridging RAM [CBRAM] or programming metallization cells [PMCs]
• CPC Class Codes: G11C 13/0023 Address circuits or decoders
• CPC Class Codes: G11C 13/0028 Word-line or row circuits
• CPC Class Codes: G11C 13/003 Cell access
• CPC Class Codes: G11C 13/004 Reading or sensing circuits or methods
• CPC Class Codes: G11C 13/0069 Writing or programming circuits or methods
• CPC Class Codes: G11C 17/146 Write once memory, i.e. allowing changing of memory content by writing additional bits
• CPC Class Codes: G11C 17/16 using electrically-fusible links
• CPC Class Codes: G11C 17/165 Memory cells which are electrically programmed to cause a change in resistance, e.g. to permit multiple resistance steps to be programmed rather than conduct to or from non-conduct change of fuses and antifuses digital stores using resistance random access memory elements G11C13/0002
• CPC Class Codes: G11C 17/18 Auxiliary circuits, e.g. for writing into memory
• CPC Class Codes: G11C 2013/0045 Read using current through the cell
• CPC Class Codes: G11C 2013/0073 Write using bi-directional cell biasing
• CPC Class Codes: G11C 2213/72 Array wherein the access device being a diode
• CPC Class Codes: G11C 2213/74 Array wherein each memory cell has more than one access device
• CPC Class Codes: G11C 29/027 in fuses
• CPC Class Codes: G11C 8/08 : Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines
• CPC Class Codes: H01L 29/785 : having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H10B 61/10 : comprising components having two electrodes, e.g. diodes or MIM elements
• CPC Class Codes: H10B 61/22 : of the field-effect transistor [FET] type
• CPC Class Codes: H10B 63/20 : comprising selection components having two electrodes, e.g. diodes
• CPC Class Codes: H10B 63/30 : comprising selection components having three or more electrodes, e.g. transistors
• CPC Class Codes: H10N 70/231 : based on solid-state phase change, e.g. between amorphous and crystalline phases, Ovshinsky effect
• CPC Class Codes: H10N 70/826 : adapted for essentially vertical current flow, e.g. sandwich or pillar type devices
• CPC Class Codes: H10N 70/8828 : Tellurides, e.g. GeSbTe

Abstract

A programmable resistive device cell using at least one MOS device as selector can be programmed or read by turning on a source junction diode of the MOS or a channel of the MOS. A programmable resistive device cell can include at least one programmable resistive element and at least one MOS device. The programmable resistive element can be coupled to a first supply voltage line. The MOS can have a source coupled to the programmable resistive element, a bulk coupled to a drain, a drain coupled to a second supply voltage line, and a gate coupled to a third supply voltage line. The programmable resistive element can be configured to be programmable or readable by applying voltages to the first, second, and/or third supply voltage lines to turn on the source junction of the MOS and/or to turn on the channel of the MOS.

Claims

1. A programmable resistive device (PRD) memory comprising:

a plurality of PRD cells, at least one of the PRD cells including at least;

at least one programmable resistive element (PRE) coupled to a first supply voltage line; and

at least one Metal-Oxide-Semiconductor (MOS) device having a source coupled to the PRE, a bulk coupled to a drain, the drain coupled to a second supply voltage line, and a gate coupled to a third supply voltage line,

wherein the PRE is configured to be programmable by applying voltages to the first, second, and/or third supply voltage lines to turn on the source junction diode or a channel of the MOS to thereby change the PRE into a different logic state.

2. A programmable resistive device memory as recited in claim 1, wherein the PRE is configured to be readable by applying voltages to the first, second, and/or third supply voltage lines to turn on the source junction diode or the channel of the MOS to thereby read the PRE resistance into a logic state.

3. A programmable resistive device memory as recited in claim 1, wherein the PRE is configured to be:

(a) programmable by applying voltages to the first, second, and/or third supply voltage lines to turn on the source junction diode of the MOS to thereby change the PRE into a different logic state, and (b) readable by applying voltages to the first, second, and third supply voltage lines to turn on the channel of the MOS to read the resistance of the PRE into a logic state.

4. A programmable resistive device memory as recited in claim 1, wherein the PRE is configured to be:

(a) programmable by applying voltages to the first, second, and/or third supply voltage lines to turn on the source junction diode of the MOS to thereby change the PRE into a one logic state, and (b) programmable by applying voltages to the first, second, and third supply voltage lines to turn on the channel of the MOS to thereby change the PRE into another logic state.

5. A programmable resistive device memory as recited in claim 1, wherein the programmable resistive element is a One-Time Programmable (OTP) element that can be programmed only once.

6. A programmable resistive device memory as recited in claim 5, wherein the OTP element is constructed from at least one of a polysilicon, silicide, silicided polysilicon, CMOS metal gate, metal interconnect, polymetal, local interconnect, metal alloy, or thermally isolated active area.

7. A programmable resistive device memory as recited in claim 5, wherein the OTP element is constructed from at least one conductive contact or via.

8. A programmable resistive device memory as recited in claim 5, wherein the OTP element is an anti-fuse fabricated by at least one contact or via with dielectrics in between, or an anti-fuse comprising of a CMOS gate and a CMOS body with gate oxide in between.

9. A programmable resistive device memory as recited in claim 1, wherein the programmable resistive element includes at least one thin film, and wherein the PRD memory is Phase-Change Memory (PCRAM), Resistive Memory (RRAM), Conductive Bridge Memory (CBRAM), or Magnetic Memory (MRAM).

10. A programmable resistive device memory as recited in claim 1, wherein the resistive element comprises a film of phase change material including at least one of Germanium (Ge), Antimony (Sb), and Tellurium (Te).

11. A programmable resistive device memory as recited in claim 1, wherein the resistive element comprises at least one metal-oxide film between metal or metal alloy electrodes.

12. A programmable resistive device memory as recited in claim 1, wherein the resistive element comprises at least one solid-state electrolyte film between metal or metal oxide electrodes.

13. A programmable resistive device memory as recited in claim 1, wherein the programmable resistive element can be programmed into different logic states depending on the directions of the current flowing through the programmable resistive element.

14. A programmable resistive device memory as recited in claim 1, wherein the programmable resistive cell is build on a thermally insolated substrate or a 3D fin structure.

15. An electronic system, comprising:

a processor; and

a programmable resistive device memory operatively connected to the processor, the programmable resistive device memory including a plurality of programmable resistive device (PRD) cells, at least one of the PRD cells comprising;

a programmable resistive element (PRE) coupled to a first supply voltage line; and

at least one Metal-Oxide-Semiconductor (MOS) device having a source coupled to the PRE, a bulk coupled to a drain, the drain coupled to a second supply voltage line, and a gate coupled to a third supply voltage line,

wherein the PRE is configured to be programmable by applying voltages to the first, second, and/or third supply voltage lines to turn on the source junction diode or a channel of the MOS to thereby change the PRE into a different logic state, and

wherein the PRE is configured to be readable by applying voltages to the first, second, and/or third supply voltage lines to turn on the source junction diode or the channel of the MOS to thereby read the PRE resistance into a logic state.

16. An electronic system as recited in claim 15, wherein the programmable resistive element is constructed from at least one of a polysilicon, silicide, silicided polysilicon, CMOS metal gate, metal interconnect, polymetal, local interconnect, metal alloy, or thermally isolated active area.

17. An electronic system as recited in claim 15, wherein the programmable resistive element includes at least one of thin films in the cells of Phase-Change Memory (PCRAM), Resistive Memory (RRAM), Conductive Bridge Memory (CBRAM), or Magnetic Memory (MRAM).

18. A method for operating a programmable resistive device memory, the method comprising:

providing a plurality of programmable resistive device cells, at least one of the programmable resistive device cells includes at least (i) a programmable resistive element coupled to a first supply voltage line; and

(ii) at least one Metal-Oxide-Semiconductor (MOS) device as a selector having a source coupled to the programmable resistive element, a bulk coupled to a drain, the drain coupled to a second supply voltage line, and a gate coupled to a third supply voltage line;

programming a logic state into at least one of the programmable resistive device cells by applying voltages to the first, the second, and/or the third supply voltage lines to turn on the source junction diode or the channel of the MOS; and

sensing a current flowing in one of the at least one programmable resistive device cells by applying voltages to the first, second and/or the third supply voltage lines to turn on the source junction diode or the channel of the MOS.

19. A method as recited in claim 18, wherein the programming is by turning on the source junction diode of the MOS and reading is by turning on the channel of the MOS.

20. A method as recited in claim 18, wherein the programming into one logic state is by turning on the source junction diode of the MOS and programming into another logic state is by turning on the channel of the MOS.

21. A method as recited in claim 18, wherein the programmable resistive element is constructed from at least one of a polysilicon, silicide, silicided polysilicon, CMOS metal gate, metal interconnect, polymetal, local interconnect, metal alloy, or thermally isolated active area.