DATA STORAGE SYSTEM WITH DYNAMIC READ THRESHOLD MECHANISM AND METHOD OF OPERATION THEREOF

• US 20150039842A1
• Filed: 08/01/2013
• Published: 02/05/2015
• Est. Priority Date: 08/01/2013
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: Smart Storage Systems Incorporated (Western Digital Corporation)
• Inventors: Fitzpatrick, James, Dancho, Mark, Higgins, James M., Ellis, Robert W.
• Granted Patent: US 9,146,850 B2
• Time in Patent Office: Days
• US Class Current: 711/154
• CPC Class Codes: G06F 12/00 Accessing, addressing or allocating within memory systems or architectures digital input from, or digital output to record carriers, e.g. to disk storage units, G06F3/06
• CPC Class Codes: G11C 11/5642 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/06 Auxiliary circuits, e.g. for writing into memory
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/3454 Arrangements for verifying correct programming or for detecting overprogrammed cells
• CPC Class Codes: G11C 16/349 Arrangements for evaluating degradation, retention or wearout, e.g. by counting erase cycles

Abstract

A system and method of operation of a data storage system includes: a memory die for determining a middle read threshold; a control unit, coupled to the memory die, for calculating a lower read threshold and an upper read threshold based on the middle read threshold and a memory element age; and a memory interface, coupled to the memory die, for reading a memory page of the memory die using the lower read threshold, the middle read threshold, or the upper read threshold for compensating for a charge variation.

Claims

1. A method of operation of a data storage system comprising:

determining a middle read threshold for a memory die;

calculating a lower read threshold and an upper read threshold based on the middle read threshold and a memory element age; and

reading a memory page of the memory die using the lower read threshold, the middle read threshold, or the upper read threshold for compensating for a charge variation.

2. The method as claimed in claim 1 further comprising:

retrieving a die read threshold from a controller database;

calculating an outlier block offset for an outlier block based on the location of the outlier block; and

modifying the lower read threshold, the middle read threshold, and the upper read threshold with the outlier block offset.

3. The method as claimed in claim 1 further comprising:

retrieving a die read threshold from a controller database;

calculating an outlier page offset for an outlier page based on the location of the outlier page; and

modifying the lower read threshold, the middle read threshold, and the upper read threshold with the outlier page offset.

4. The method as claimed in claim 1 further comprising modifying the lower read threshold, the middle read threshold, and the upper read threshold based on a retention time.

5. The method as claimed in claim 1 further comprising modifying the lower read threshold, the middle read threshold, and the upper read threshold based on a read disturb count.

6. A method of operation of a data storage system comprising:

calculating a middle read threshold for a memory die;

retrieving a memory element age for the memory die;

calculating a lower read threshold and an upper read threshold based on the middle read threshold and the memory element age; and

reading a memory page of the memory die using the lower read threshold, the middle read threshold, or the upper read threshold for compensating for a charge variation.

7. The method as claimed in claim 6 further comprising:

detecting a power up event;

detecting a first test threshold having a bit error rate after detecting the power up event;

detecting a second test threshold having another of the bit error rate greater than the bit error rate of the first test threshold, the second test threshold lower than the first test threshold;

determining a power up offset for a memory die based on the first test threshold; and

modifying the lower read threshold, the middle read threshold, or the upper read threshold based on the power up offset.

8. The method as claimed in claim 6 further comprising:

detecting a scheduling event based on a program erase cycle count meeting or exceeding a program erase cycle count threshold;

calculating a program erase offset based on the program erase cycle count; and

modifying the lower read threshold, the middle read threshold, or the upper read threshold based on the program erase offset.

9. The method as claimed in claim 6 further comprising:

detecting a scheduling event based on an error count meeting or exceeding an error count threshold;

calculating an error count offset based on the error count; and

modifying the lower read threshold, the middle read threshold, or the upper read threshold based on the error count offset.

10. The method as claimed in claim 6 wherein calculating the memory element age includes setting the memory element age to the program erase cycle count.

11. A data storage system comprising:

a memory die for determining a middle read threshold;

a control unit, coupled to the memory die, for calculating a lower read threshold and an upper read threshold based on the middle read threshold and a memory element age; and

a memory interface, coupled to the memory die, for reading a memory page of the memory die using the lower read threshold, the middle read threshold, or the upper read threshold for compensating for a charge variation.

12. The system as claimed in claim 11 further comprising:

a controller database, coupled to the control unit, for retrieving a die read threshold; and

an outlier block adjustment module, coupled to the control unit, for calculating an outlier block offset for an outlier block based on the location of the outlier block and for modifying the lower read threshold, the middle read threshold, or the upper read threshold with the outlier block offset.

13. The system as claimed in claim 11 further comprising:

a controller database, coupled to the control unit, for retrieving a die read threshold; and

an outlier page adjustment module, coupled to the control unit, for calculating an outlier page offset for an outlier page based on the location of the outlier page and for modifying the lower read threshold, the middle read threshold, or the upper read threshold with the outlier page offset.

14. The system as claimed in claim 11 wherein the lower read threshold, the middle read threshold, or the upper read threshold are modified based on a retention time.

15. The system as claimed in claim 11 wherein the lower read threshold, the middle read threshold, or the upper read threshold are modified based on a read disturb count.

16. The system as claimed in claim 11 further comprising an array controller, coupled to the memory die, for retrieving the memory element age of the memory die.

17. The system as claimed in claim 16 further comprising:

a power up event module, coupled to the control unit, for detecting a power up event;

a find read thresholds module, coupled to the power up event module, for detecting a first test threshold having a bit error rate and for detecting a second test threshold having another of the bit error rate greater than the bit error rate of the first test threshold with the second test threshold lower than the first test threshold; and

a calculate power up offset module, coupled to the find read thresholds module, for determining a power up offset for the memory die based on the first test threshold and for modifying the lower read threshold, the middle read threshold, or the upper read threshold based on the power up offset.

18. The system as claimed in claim 16 further comprising:

a program erase event module, coupled to the control unit, for detecting a scheduling event based on a program erase cycle count meeting or exceeding a program erase cycle count threshold; and

a calculate program erase offset module, coupled to the program erase event module, for calculating a program erase offset based on the program erase cycle count and for modifying the lower read threshold, the middle read threshold, or the upper read threshold based on the program erase offset.

19. The system as claimed in claim 16 further comprising:

an error count event module, coupled to the control unit, for detecting a scheduling event based on an error count meeting or exceeding an error count threshold; and

an calculate error count offset module, coupled to the error count event module, for calculating an error count offset based on the error count and for modifying the lower read threshold, the middle read threshold, or the upper read threshold based on the error count offset.

20. The system as claimed in claim 16 further comprising an initial mapping module, coupled to the control unit, for calculating the memory element age includes setting the memory element age to a program erase cycle count.