Trench Power MOSFET
First Claim
1. A method comprising:
- forming a first trench in a semiconductor region, wherein the semiconductor region is of a first conductivity type;
forming an implantation mask extending into the trench and covering edges of the trench;
performing a tilt implantation to form a Doped Drain (DD) region in the semiconductor region, wherein the DD region is of the first conductivity type;
etching the semiconductor region to extend the trench further down into the semiconductor region, wherein the etching is anisotropic, with portions of the DD region located on opposite sides of the trench;
after the etching, forming a first dielectric layer lining a bottom and sidewalls of the trench;
forming a field plate in the trench and over a bottom portion of the first dielectric layer;
forming a second dielectric layer over the field plate; and
forming a main gate in the trench and over the second dielectric layer.
0 Assignments
0 Petitions
Accused Products
Abstract
A device includes a semiconductor region of a first conductivity type, a trench extending into the semiconductor region, and a conductive field plate in the trench. A first dielectric layer separates a bottom and sidewalls of the field plate from the semiconductor region. A main gate is disposed in the trench and overlapping the field plate. A second dielectric layer is disposed between and separating the main gate and the field plate from each other. A Doped Drain (DD) region of the first conductivity type is under the second dielectric layer, wherein an edge portion of the main gate overlaps the DD region. A body region includes a first portion at a same level as a portion of the main gate, and a second portion at a same level as, and contacting, the DD region, wherein the body region is of a second conductivity type opposite the first conductivity type.
-
Citations
20 Claims
-
1. A method comprising:
-
forming a first trench in a semiconductor region, wherein the semiconductor region is of a first conductivity type; forming an implantation mask extending into the trench and covering edges of the trench; performing a tilt implantation to form a Doped Drain (DD) region in the semiconductor region, wherein the DD region is of the first conductivity type; etching the semiconductor region to extend the trench further down into the semiconductor region, wherein the etching is anisotropic, with portions of the DD region located on opposite sides of the trench; after the etching, forming a first dielectric layer lining a bottom and sidewalls of the trench; forming a field plate in the trench and over a bottom portion of the first dielectric layer; forming a second dielectric layer over the field plate; and forming a main gate in the trench and over the second dielectric layer. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12)
-
-
13. A method comprising:
-
epitaxially growing an epitaxy semiconductor region of a first conductivity type; forming a first trench in the epitaxy semiconductor region; forming an implantation mask extending into the trench and covering edge portions of the trench; performing a tilt implantation to form a Doped Drain (DD) region in the epitaxy semiconductor region, wherein the DD region comprises portions overlapped by the implantation mask, and wherein the DD region is of a first conductivity type; etching the epitaxy semiconductor region to extend the trench further down into the epitaxy semiconductor region, wherein the etching is performed using the implantation mask as an etching mask; after the etching, forming a first dielectric layer lining the trench; forming a field plate in the trench and over the first dielectric layer, wherein the field plate comprises a bottom and sidewalls contacting the first dielectric layer; forming a second dielectric layer over the field plate; and forming a main gate in the trench and over the second dielectric layer. - View Dependent Claims (14, 15, 16, 17)
-
-
18. A method comprising:
-
forming a field plate in a semiconductor region of a first conductivity type; forming a first dielectric layer comprising first portions on opposite sides the field plate, and second portions underlying the field plate; forming Doped Drain (DD) regions on opposite sides of the first dielectric layer, wherein the DD region is of the first conductivity type; performing an implantation to form a body region in the semiconductor region, wherein the body region is of a second conductivity type opposite to the first conductivity type; forming a second dielectric layer over the field plate; and forming a main gate over the second dielectric layer, wherein the DD regions comprise a portion overlapped by the main gate, and the portion of the DD regions comprises a sidewall contacting a sidewall of the first dielectric layer. - View Dependent Claims (19, 20)
-
Specification