SEMICONDUCTOR DEVICE WITH ENHANCED MOBILITY AND METHOD

• US 20150054068A1
• Filed: 10/02/2014
• Published: 02/26/2015
• Est. Priority Date: 06/13/2011
• Status: Active Grant

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Inventors: Grivna, Gordon M., Hossain, Zia, Huang, Kirk K., Padmanabhan, Balaji, Robb, Francine Y., Venkatraman, Prasad
• Granted Patent: US 9,450,091 B2
• Time in Patent Office: Days
• US Class Current: 257/331
• CPC Class Codes: H01L 29/0869 Shape cell layout H01L29/0696
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/41 characterised by their shape, relative sizes or dispositions
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/42376 characterised by the length or the sectional shape
• CPC Class Codes: H01L 29/456 on silicon
• CPC Class Codes: H01L 29/66666 Vertical transistors H01L29/66712, H01L29/66742 take precedence
• CPC Class Codes: H01L 29/66727 with a step of recessing the source electrode
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/7827 Vertical transistors H01L29/7802, H01L29/78642 take precedence
• CPC Class Codes: H01L 29/7842 means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate variation of the composition of the channel H01L29/1054
• CPC Class Codes: H01L 29/7845 the means being a conductive material, e.g. silicided S/D or Gate
• CPC Class Codes: H01L 29/7848 the means being located in the source/drain region, e.g. SiGe source and drain

Abstract

In one embodiment, a vertical insulated-gate field effect transistor includes a feature embedded within a control electrode. The feature is placed within the control electrode to induce stress within predetermined regions of the transistor.

Claims

1. A semiconductor device comprising:

a region of semiconductor material having a major surface;

a trench control structure in the region of semiconductor material including a gate dielectric layer adjacent sidewall surfaces of the trench control structure and a gate electrode comprising a first conductive material adjoining the gate dielectric layer;

a body region within the region of semiconductor material and adjacent the trench control structure, where the trench control structure is configured to provide a channel region within the body region, where the channel region includes a source end and a drain end;

a source region within the body region having a first side adjacent the trench control structure and a second side opposite to the first side; and

a first feature comprising a material other than the first conductive material completely embedded within the gate electrode, where the first feature is configured to induce stress within portions of the channel region.

2. The device of claim 1, where the first feature comprises dielectric material.

4. The device of claim 1, where at least portion of the first feature comprises a silicide material and the gate electrode comprises a polycrystalline semiconductor material.

5. The device of claim 1, where the trench control structure further includes a shield electrode below the gate electrode, where the shield electrode is separated from the region of semiconductor material by a dielectric layer.

6. The device of claim 5 further comprising a second feature within the shield electrode, where the second feature is configured to induce stress within a drift region of the semiconductor device, and where at least one of the first and second features comprises a dielectric material.

8. The device of claim 1 further comprising a second feature adjoining the second side of the source region, where the second feature is configured to induce stress in proximity to the source end of the channel region.

9. The device of claim 1 further comprising second features adjacent to opposing corners of the gate electrode in proximity to the drain end of the channel region and configured to induce stress within the drain end of the channel region.

3. (canceled)

7. (canceled)

10. (canceled)

11. (canceled)

12. An insulating gate field effect transistor structure having enhanced mobility comprising:

a region of semiconductor material having a first conductivity type, a first major surface, and a second major surface opposing the first major surface, where the region of semiconductor material at the second major surface is configured as a drain region;

a trench structure within the region of semiconductor material comprising a shield electrode in a lower portion of a trench, where the shield electrode is separated from the region of semiconductor material by a first dielectric layer;

a gate electrode in an upper portion of the trench, wherein the gate electrode is separated from the region of semiconductor material by a second dielectric layer and separated from the shield electrode by a third dielectric layer;

a body region having a second conductivity type opposite to the first conductivity type in the region of semiconductor material and adjacent to the trench structure, where the gate electrode is configured to form a channel region within the body region;

a source region of the first conductivity type in spaced relationship with the body region having a first side adjacent to the trench structure and a second side opposite to the first side; and

a first region within the gate electrode and comprising a silicide material that propagates stress within the region of semiconductor material adjacent to the trench control structure to provide the enhanced mobility.

15. The structure of claim 12 further comprising a second region within the shield electrode and comprising a material configured to propagates stress within a drift region of the structure to provide the enhanced mobility.

16. The structure of claim 15, where the second region comprises a silicide.

17. The structure of claim 16 further comprising a third region overlying the shield electrode and a fourth region overlying the gate electrode, where both the third and fourth regions comprise a material configured to propagate stress within the region of semiconductor material adjacent to the trench structure.

18. The structure of claim 12 further comprising a second region adjacent to the second side of the source region and comprising a material that propagates stress in proximity to a source end of the channel region.

13-14. -14. (canceled)

19-39. -39. (canceled)

40. A method of forming a semiconductor device comprising:

providing a region of semiconductor material having a trench extending from a major surface and having an isolated shield electrode structure in a lower portion of the trench and a gate dielectric layer adjacent sidewalls of the trench;

forming a first conductive layer adjacent the gate dielectric layer in the trench, the first conductive layer configured as part of a gate electrode structure;

forming a stress inducing structure within the trench adjacent the first conductive layer, wherein the stress inducing structure and the first conductive layer comprises different materials; and

forming a second conductive layer adjacent the stress inducing layer, the second conductive layer configured as another part of the gate electrode structure.

41. The method of claim 40 further comprising forming a stress inducing layer along portions of the first conductive layer.

42. The method of claim 41, wherein forming the stress inducing layer comprises forming a layer comprising a silicide.

43. The method of claim 42, wherein forming the stress inducing structure includes forming a stress inducing structure comprising a dielectric.

44. The method of claim 40, wherein forming the first conductive layer comprises:

forming a doped polycrystalline semiconductor layer; and

removing a lower portion of the doped polycrystalline semiconductor layer adjacent the insulated shield electrode to form doped polycrystalline spacers.

45. The method of claim 40, wherein forming the stress inducing structure includes recessing the stress inducing structure within the trench.

46. The method of claim 40, wherein forming the stress inducing structure includes forming the stress inducing structure comprising a conductive material.

47. The method of claim 40, wherein forming the stress inducing structure includes forming the stress inducing structure comprising a silicide material.