FLOATING POINT IMAGE SENSORS WITH TILE-BASED MEMORY

• US 20150055001A1
• Filed: 08/13/2014
• Published: 02/26/2015
• Est. Priority Date: 08/23/2013
• Status: Active Grant

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Aptina Imaging Corporation (ON Semiconductor Corporation)
• Inventors: Bock, Nikolai
• Granted Patent: US 9,307,172 B2
• Time in Patent Office: Days
• US Class Current: 348/308
• CPC Class Codes: H04N 25/57 Control of the dynamic range
• CPC Class Codes: H04N 25/75 Circuitry for providing, modifying or processing image signals from the pixel array
• CPC Class Codes: H04N 25/77 Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components
• CPC Class Codes: H04N 25/771 comprising storage means other than floating diffusion
• CPC Class Codes: H04N 25/772 comprising A/D, V/T, V/F, I/T or I/F converters
• CPC Class Codes: H04N 25/778 comprising amplifiers shared between a plurality of pixels, i.e. at least one part of the amplifier must be on the sensor array itself

Abstract

An image sensor may include an array of image sensor pixels arranged in rows and columns. Each image pixel arranged along a given column may be coupled to analog-to-digital converter (ADC) circuitry that is capable of converting analog pixel signals into a digital floating point equivalent representation. The ADC circuitry may be configured to obtain an illumination value during an auto exposure period. The illumination value, which serves as an exponent value, can be stored as tile data in a tile column memory circuit. During actual readout, the ADC circuitry may be configured to perform mantissa conversion. During mantissa conversion, the ADC circuitry may use a reference voltage value that is adjusted based on the tile data. A mantissa value that is obtained during the mantissa conversion may then be combined with the exponent value for that tile to yield a final floating number point for that image pixel.

Claims

1. An image sensor, comprising:

an array of image sensor pixels arranged in rows and columns, wherein the array is grouped into tiles each of which includes multiple rows and columns of image sensor pixels;

a first column output line that is coupled to a first column of image sensor pixels in a given tile;

a second column output line that is coupled to a second column of image sensor pixels in the given tile;

first readout circuitry that is coupled to the first column output line;

second readout circuitry that is coupled to the second column output line; and

a tile column memory circuit that is shared between the first and second readout circuitries.

2. The image sensor defined in claim 1, wherein the first readout circuitry includes a first analog-to-digital converter (ADC), and wherein the second readout circuitry includes a second analog-to-digital converter (ADC).

3. The image sensor defined in claim 2, wherein the first readout circuitry further includes a first digital-to-analog converter (DAC), and wherein the second readout circuitry further includes a second digital-to-analog converter (DAC).

4. The image sensor defined in claim 3, wherein the first and second DACs supply reference voltages having a voltage level that is adjusted based on data stored in the tile column memory circuit.

5. The image sensor defined in claim 1, wherein the first readout circuitry receives analog pixel signals from the array of image sensor pixels and converts the analog pixel signals into floating point numbers.

6. The image sensor defined in claim 3, wherein the first DAC comprises an array of binary weighted capacitors, and wherein each capacitor in the array of binary weighted capacitors is selectively switched into use using respective switches.

7. The image sensor defined in claim 6, further comprising:

a control register that receives input signals from the tile column memory circuit and that generates control signals for selectively activating the respective switches.

8. The image sensor defined in claim 7, wherein the control register comprises:

a digital latch having an input and an output;

a first logic gate that is coupled to the input of the digital latch; and

a second logic gate that is coupled to the output of the digital latch.

9. The image sensor defined in claim 8, wherein the digital latch comprises a set-reset latch.

10. The image sensor defined in claim 8, wherein the first and second logic gates comprises logic AND gates.

11. A method of operating an image sensor that includes an array of image sensor pixels arranged in rows and columns, wherein the array is grouped into tiles each of which includes multiple rows and columns of image sensor pixels, the method comprising:

with a plurality of readout circuits, receiving pixel signals from image sensor pixels that are part of a given tile; and

with a tile column memory circuit that is shared among the plurality of readout circuits, outputting bits that control the plurality of readout circuit.

12. The method defined in claim 11, wherein the plurality of readout circuits include analog-to-digital converters (ADCs) and associated digital-to-analog converters (DACs), wherein the DACs supply reference voltages to the ADCs, and wherein the reference voltages that are supplied from the DACs to the ADCs are adjusted based on the bits stored in the tile column memory circuit.

13. The method defined in claim 11, further comprising:

obtaining the bits that are stored in the tile column memory circuit by performing auto exposure operations.

14. The method defined in claim 11, further comprising:

with the plurality of readout circuits, converting the pixel signals into floating point numbers.

15. The method defined in claim 14, wherein the tile column memory circuit stores exponent information, wherein the plurality of readout circuits generate mantissa information from the received pixel signals, and wherein the exponent information is combined with the mantissa information to yield the floating point numbers.

16. A system, comprising:

a central processing unit;

memory;

input-output circuitry; and

an imaging device, wherein the imaging device comprises;

an array of image sensor pixels arranged in rows and columns, wherein the array is grouped into tiles each of which includes multiple rows and columns of image sensor pixels;

a plurality of readout circuits that receive pixel signals from image sensor pixels that are part of a given tile; and

a tile column memory circuit that is shared among the plurality of readout circuits and that outputs bits for controlling the plurality of readout circuit.

17. The system defined in claim 16, wherein the plurality of readout circuits include analog-to-digital converters (ADCs) and associated digital-to-analog converters (DACs), wherein the DACs supply reference voltages to the ADCs, and wherein the reference voltages that are supplied from the DACs to the ADCs are adjusted based on the bits stored in the tile column memory circuit.

18. The system defined in claim 16, wherein the plurality of readout circuits convert the received pixel signals into floating point numbers.

19. The system defined in claim 18, wherein the tile column memory circuit stores exponent information, wherein the plurality of readout circuits generate mantissa information from the received pixel signals, and wherein the exponent information is combined with the mantissa information to obtain the floating point numbers.

20. The system defined in claim 17, wherein the at least one of the DACs comprises an array of binary weighted capacitors, and wherein only one capacitor in the array of binary weighted capacitors is selectively switched into use based on the bits stored in the tile column memory.