SEMICONDUCTOR STRUCTURE AND METHOD OF FORMING THE SAME

• US 20150061041A1
• Filed: 09/03/2013
• Published: 03/05/2015
• Est. Priority Date: 09/03/2013
• Status: Active Grant

• Current Assignee: United Microelectronics Corporation
• Original Assignee: United Microelectronics Corporation
• Inventors: Lin, Chun-Hsien, Chen, Min-Hsien
• Granted Patent: US 9,384,984 B2
• Time in Patent Office: Days
• US Class Current: 257/410
• CPC Class Codes: H01L 21/28088 the final conductor layer next to the insulator being a composite, e.g. TiN
• CPC Class Codes: H01L 21/2855 by physical means, e.g. sputtering, evaporation H01L21/28518 - H01L21/28537 and H01L21/28568 take precedence
• CPC Class Codes: H01L 21/823842 gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures
• CPC Class Codes: H01L 29/165 in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 29/4966 the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2 H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H01L 29/513 the variation being perpendicular to the channel plane
• CPC Class Codes: H01L 29/517 the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate H01L29/518 takes precedence
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/66575 where the source and drain or source and drain extensions are self-aligned to the sides of the gate H01L29/66606 takes precedence
• CPC Class Codes: H01L 29/66636 with source or drain recessed by etching or first recessed by etching and then refilled

Abstract

A method of forming a semiconductor device is disclosed. A substrate having a dielectric layer thereon is provided. The dielectric layer has a gate trench therein and a gate dielectric layer is formed on a bottom of the gate trench. A work function metal layer and a top barrier layer are sequentially formed in the gate trench. A treatment is performed to the top barrier layer so as to form a silicon-containing top barrier layer. A low-resistivity metal layer is formed in the gate trench.

Claims

1. A method of forming a semiconductor device, comprising:

providing a substrate, wherein the substrate has a dielectric layer thereon, the dielectric layer has a gate trench therein and a gate dielectric layer is formed on a bottom of the gate trench;

sequentially forming a work function metal layer and a top barrier layer in the gate trench;

performing a treatment to the top barrier layer so as to form a silicon-containing top barrier layer; and

forming a low-resistivity metal layer in the gate trench.

2. The method of claim 1, wherein the top barrier layer is a stacked structure comprising at least one N-rich TiN layer and at least one Ti-rich TiN layer, and an upmost layer of the stacked structure is a Ti-rich TiN layer.

3. The method of claim 2, wherein the treatment transforms a portion of the upmost Ti-rich TiN layer into a TiSiN layer.

4. The method of claim 2, wherein the treatment completely transforms the upmost Ti-rich TiN layer into a TiSiN layer.

5. The method of claim 2, wherein the treatment comprises introducing a silicon-containing gas and a nitrogen-containing gas to stuff grain boundaries of the upmost Ti-rich TiN layer.

6. The method of claim 1, wherein the treatment comprises a silicification treatment and a nitridation treatment.

7. The method of claim 6, wherein a gas used in the silicification treatment comprises silane (SiH₄) and a gas used in the nitridation treatment comprises ammonia (NH₃).

8. The method of claim 1, wherein the work function metal layer has a substantially planar surface on the bottom of the gate trench.

9. The method of claim 8, wherein a method of achieving the substantially planar surface of the work function metal layer comprises performing a radio frequency PVD (RFPVD) process.

10. The method of claim 1, further comprising forming a bottom barrier layer between the gate dielectric layer and the work function metal layer.

11. The method of claim 1, wherein the gate dielectric layer is formed before the step of forming the dielectric layer.

12. The method of claim 1, wherein the gate dielectric layer is formed after the step of forming the gate trench.

13. A semiconductor structure, comprising:

a substrate;

a dielectric layer, disposed on the substrate and having two gate trenches therein;

two gate dielectric layers, at least disposed on a bottom of the two gate trenches;

a low-resistivity metal layer, disposed in the two gate trenches;

a work function metal layer, disposed between the low-resistivity metal layer and the gate dielectric layer; and

a silicon-containing top barrier layer, disposed between the low-resistivity metal layer and the work function metal layer, wherein the material of the silicon-containing top barrier layers in both trenches are same.

14. The semiconductor structure of claim 13, wherein the silicon-containing top barrier layer comprises titanium silicon nitride (TiSiN).

15. The semiconductor structure of claim 13, further comprising at least one top barrier layer disposed between the work function metal layer and the silicon-containing top barrier layer.

16. The semiconductor structure of claim 15, wherein the top barrier layer is a Ti-rich TiN layer.

17. The semiconductor structure of claim 15, wherein the top barrier layer is an N-rich TiN layer.

18. The semiconductor structure of claim 15, wherein each of the work function metal layer, the at least one top barrier layer and the silicon-containing top barrier layer has a substantially planar surface on the bottom surface of the gate trench.

19. The semiconductor structure of claim 13, further comprising a bottom barrier layer disposed between the gate dielectric layer and the work function metal layer.

20. The semiconductor structure of claim 13, wherein the gate dielectric layer is further disposed on a sidewall of the gate trench.