MULTI-CORE HARDWARE SEMAPHORE
First Claim
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1. A microprocessor, comprising:
- a plurality of processing cores;
a resource, shared by the plurality of processing cores; and
a hardware semaphore, readable and writeable by each of the plurality of processing cores within a non-architectural address space;
wherein each of the plurality of processing cores is configured to write to the hardware semaphore to request ownership of the shared resource and to read from the hardware semaphore to determine whether or not the ownership was obtained; and
wherein each of the plurality of processing cores is configured to write to the hardware semaphore to relinquish ownership of the shared resource.
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Abstract
A microprocessor includes a plurality of processing cores, a resource shared by the plurality of processing cores, and a hardware semaphore readable and writeable by each of the plurality of processing cores within a non-architectural address space. Each of the plurality of processing cores is configured to write to the hardware semaphore to request ownership of the shared resource and to read from the hardware semaphore to determine whether or not the ownership was obtained. Each of the plurality of processing cores is configured to write to the hardware semaphore to relinquish ownership of the shared resource.
11 Citations
22 Claims
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1. A microprocessor, comprising:
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a plurality of processing cores; a resource, shared by the plurality of processing cores; and a hardware semaphore, readable and writeable by each of the plurality of processing cores within a non-architectural address space; wherein each of the plurality of processing cores is configured to write to the hardware semaphore to request ownership of the shared resource and to read from the hardware semaphore to determine whether or not the ownership was obtained; and wherein each of the plurality of processing cores is configured to write to the hardware semaphore to relinquish ownership of the shared resource. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11)
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12. A method for operating a microprocessor having a plurality of processing cores and a resource shared by the plurality of processing cores, the method comprising:
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by each of the plurality of processing cores, writing to a hardware semaphore to request ownership of the shared resource, wherein the hardware semaphore is readable and writeable by each of the plurality of processing cores within a non-architectural address space; by each of the plurality of processing cores, reading from the hardware semaphore to determine whether or not the ownership was obtained; by each of the plurality of processing cores, accessing the shared resource only if ownership was obtained; and by each of the plurality of processing cores, writing to the hardware semaphore to relinquish ownership of the shared resource after ownership was obtained. - View Dependent Claims (13, 14, 15, 16, 17, 18, 19, 20)
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21. A computer program product encoded in at least one non-transitory computer usable medium for use with a computing device, the computer program product comprising:
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computer usable program code embodied in said medium, for specifying a microprocessor, the computer usable program code comprising; first program code for specifying a plurality of processing cores; second program code for specifying a resource, shared by the plurality of processing cores; and third program code for specifying a hardware semaphore, readable and writeable by each of the plurality of processing cores within a non-architectural address space; and wherein each of the plurality of processing cores is configured to write to the hardware semaphore to request ownership of the shared resource and to read from the hardware semaphore to determine whether or not the ownership was obtained; and wherein each of the plurality of processing cores is configured to write to the hardware semaphore to relinquish ownership of the shared resource. - View Dependent Claims (22)
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Specification