PROPAGATION OF MICROCODE PATCHES TO MULTIPLE CORES IN MULTICORE MICROPROCESSOR
First Claim
1. A microprocessor, comprising:
- a plurality of processing cores, wherein each of the plurality of processing cores executes microcode and comprises hardware to patch the microcode;
wherein a first core of the plurality of processing cores is configured to;
encounter an instruction that instructs the first core to apply a microcode patch; and
in response to encountering the instruction;
inform each core of the other of the plurality of processing cores of the microcode patch; and
apply the microcode patch to the hardware of the first core; and
wherein each core of the plurality of processing cores other than the first core is configured to apply the microcode patch to the hardware of the core, in response to being informed by the first core.
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Accused Products
Abstract
A microprocessor includes a plurality of processing cores, wherein each of the plurality of processing cores executes microcode and comprises hardware to patch the microcode. A first core of the plurality of processing cores is configured to encounter an instruction that instructs the first core to apply a microcode patch. The first core of the plurality of processing cores is further configured to, in response to encountering the instruction, inform each core of the other of the plurality of processing cores of the microcode patch and apply the microcode patch to the hardware of the first core. Each core of the plurality of processing cores other than the first core is configured to apply the microcode patch to the hardware of the core, in response to being informed by the first core.
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Citations
22 Claims
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1. A microprocessor, comprising:
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a plurality of processing cores, wherein each of the plurality of processing cores executes microcode and comprises hardware to patch the microcode; wherein a first core of the plurality of processing cores is configured to; encounter an instruction that instructs the first core to apply a microcode patch; and in response to encountering the instruction; inform each core of the other of the plurality of processing cores of the microcode patch; and apply the microcode patch to the hardware of the first core; and wherein each core of the plurality of processing cores other than the first core is configured to apply the microcode patch to the hardware of the core, in response to being informed by the first core. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13)
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14. A method to be performed in a microprocessor having a plurality of processing cores, wherein each of the plurality of processing cores executes microcode and comprises hardware to patch the microcode, the method comprising:
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encountering, by a first core of the plurality of processing cores, an instruction that instructs the first core to apply a microcode patch; informing, by the first core, each core of the other of the plurality of processing cores of the microcode patch, in response to encountering the instruction; applying, by the first core, the microcode patch to the hardware of the first core, in response to encountering the instruction; and applying, by each core of the plurality of processing cores other than the first core, the microcode patch to the hardware of the core, in response to being informed by the first core. - View Dependent Claims (15, 16, 17, 18, 19, 20, 21)
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22. A computer program product encoded in at least one non-transitory computer usable medium for use with a computing device, the computer program product comprising:
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computer usable program code embodied in said medium, for specifying a microprocessor, the computer usable program code comprising; program code for specifying a plurality of processing cores, wherein each of the plurality of processing cores executes microcode and comprises hardware to patch the microcode; wherein a first core of the plurality of processing cores is configured to; encounter an instruction that instructs the first core to apply a microcode patch; and in response to encountering the instruction; inform each core of the other of the plurality of processing cores of the microcode patch; and apply the microcode patch to the hardware of the first core; and wherein each core of the plurality of processing cores other than the first core is configured to apply the microcode patch to the hardware of the core, in response to being informed by the first core.
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Specification