NONVOLATILE MEMORY SYSTEMS WITH EMBEDDED FAST READ AND WRITE MEMORIES

• US 20150070991A1
• Filed: 07/18/2014
• Published: 03/12/2015
• Est. Priority Date: 10/24/2007
• Status: Active Grant

• Current Assignee: RPX Corporation
• Original Assignee: Si-Flash LLC (Brian Yates)
• Inventors: Rao, G. R. Mohan
• Granted Patent: US 9,257,184 B2
• Time in Patent Office: Days
• US Class Current: 365/185.08
• CPC Class Codes: G06F 12/10 Address translation
• CPC Class Codes: G06F 2212/205 Hybrid memory, e.g. using both volatile and non-volatile memory
• CPC Class Codes: G06F 2212/214 Solid state disk
• CPC Class Codes: G11C 11/02 using magnetic elements
• CPC Class Codes: G11C 11/225 Auxiliary circuits
• CPC Class Codes: G11C 13/0021 Auxiliary circuits
• CPC Class Codes: G11C 14/00 Digital stores characterised by arrangements of cells having volatile and non-volatile storage properties for back-up when the power is down
• CPC Class Codes: G11C 14/0018 whereby the nonvolatile element is an EEPROM element, e.g. a floating gate or metal-nitride-oxide-silicon [MNOS] transistor
• CPC Class Codes: G11C 16/06 Auxiliary circuits, e.g. for writing into memory
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 7/1006 Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
• CPC Class Codes: G11C 7/1084 Data input buffers, e.g. comprising level conversion circuits, circuits for adapting load

Abstract

A nonvolatile memory system is described with novel architecture coupling nonvolatile storage memory with random access volatile memory. New commands are included to enhance the read and write performance of the memory system.

Claims

1. A nonvolatile memory system comprising:

a nonvolatile memory for storage arranged in multiple blocks for access;

coupled to a volatile random access memory for read and write operations; and

wherein the coupled volatile random access memory and nonvolatile memory for storage are controlled by one or more controllers.

2. The nonvolatile memory system of claim 1 wherein the nonvolatile memory system is coupled to a central processing unit.

3. The nonvolatile memory system of claim 2 wherein the nonvolatile memory for storage is a floating gate flash memory.

4. The nonvolatile memory system of claim 2 wherein the nonvolatile memory for storage is a phase change memory.

5. The nonvolatile memory system of claim 2 wherein the nonvolatile memory for storage is a magnetic memory.

6. The nonvolatile memory system of claim 2 wherein the nonvolatile memory for storage is a ferroelectric memory.

7. The nonvolatile memory system of claim 2 wherein the nonvolatile memory for storage is a molecular memory.

8. The nonvolatile memory system of claim 2 wherein the volatile random access memory is a SRAM with at least one port for read and write access.

9. The nonvolatile memory system of claim 2 wherein the volatile random access memory is a dynamic random access memory with at least one port for read and write access.

10. The nonvolatile memory system of claim 2 wherein the volatile random access memory is a pseudo static RAM with at least one port for read and write access.

11. The nonvolatile memory system of claim 2 wherein each block of the nonvolatile memory for storage has one or more pages of stored data accessible through the coupled volatile random access memory.

12. The nonvolatile memory system of claim 11 wherein the pages are randomly addressable and accessible.

13. The nonvolatile memory system of claim 11 wherein the pages are serially addressable and accessible.

14. The nonvolatile memory system of claim 11 wherein the pages are randomly and serially addressable and accessible.

15. The nonvolatile memory system of claim 11 wherein each page of a block can be substituted on the fly for any other page of a different block through address mapping.

16. The nonvolatile memory system of claim 12 wherein each of the randomly addressable and accessible pages is capable of addressing at least one bit in each access.