PIXEL STRUCTURE AND FABRICATING METHOD THEREOF

• US 20150076486A1
• Filed: 11/20/2013
• Published: 03/19/2015
• Est. Priority Date: 09/17/2013
• Status: Active Grant

• Current Assignee: HannStar Display Corporation
• Original Assignee: HannStar Display Corporation
• Inventors: Hu, Hsien-Tang, Chao, Chang-Ming, Kang, Mu-Kai, Lai, Jui-Chi
• Granted Patent: US 9,064,978 B2
• Time in Patent Office: Days
• US Class Current: 257/43
• CPC Class Codes: G02F 1/134363 for applying an electric field parallel to the substrate, i.e. in-plane switching [IPS]
• CPC Class Codes: G02F 1/136227 Through-hole connection of the pixel electrode to the active element through an insulation layer
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52
• CPC Class Codes: H01L 29/6675 Amorphous silicon or polysilicon transistors
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
• CPC Class Codes: H01L 33/0041 characterised by field-effect operation

Abstract

The pixel structure includes a scan line, a data line, a thin-film transistor, a first electrode layer, a protective layer and a second electrode layer. The thin-film transistor is electrically connected to the scan line and the data line, and includes a gate, an oxide semiconductor layer, an insulating layer, a source and a drain. The first electrode layer is in the same layer as the oxide semiconductor layer, and is surrounded by the scan line and the data line. The second electrode layer is located on the first electrode layer, and the protective layer is located between the first electrode layer and the second electrode layer, wherein one of the first and second electrode layers is electrically connected to the thin-film transistor, and the other is connected to a common voltage. The second electrode layer includes a plurality of slits exposing an area of the first electrode layer.

Claims

1. A pixel structure characterized by comprising:

a scan line and a data line, disposed on a substrate;

a thin-film transistor disposed on the substrate and electrically connected to the scan line and the data line, the thin-film transistor comprising;

a gate disposed on the substrate;

an oxide semiconductor layer disposed on the gate;

an insulating layer covering a channel region of the oxide semiconductor layer; and

a source and a drain, disposed on the insulating layer and respectively electrically connected to the oxide semiconductor layer;

a first electrode layer in the same layer as the oxide semiconductor layer, surrounded by the scan line and the data line;

a protective layer covering the source, the drain, the oxide semiconductor layer, the first electrode layer and the substrate; and

a second electrode layer disposed on the first electrode layer, the protective layer being located between the first electrode layer and the second electrode layer, wherein one of the first and second electrode layers is electrically connected to the thin-film transistor, and the other is connected to a common voltage, and wherein the second electrode layer comprises a plurality of slits exposing an area of the first electrode layer.

2. The pixel structure according to claim 1, wherein the first electrode layer is electrically connected to the thin-film transistor, and the second electrode layer is connected to the common voltage.

3. The pixel structure according to claim 2, wherein the first electrode layer is in direct contact with the drain of the thin-film transistor, and the protective layer completely covers the drain.

4. The pixel structure according to claim 1, wherein the second electrode layer is electrically connected to the thin-film transistor, and the first electrode layer is connected to the common voltage.

5. The pixel structure according to claim 4, wherein the protective layer has a contact opening exposing the drain, and the second electrode layer is filled into the contact opening to be in contact with the drain of the thin-film transistor.

6. The pixel structure according to claim 1, further comprising a gate insulating layer covering the gate and located between the gate and the oxide semiconductor layer.

7. The pixel structure according to claim 1, wherein materials of the oxide semiconductor layer comprise indium gallium zinc oxide (IGZO), indium tin zinc oxide (ITZO), indium gallium oxide (IGO) or indium zinc oxide (IZO).

8. A fabrication method of a pixel structure, characterized by comprising:

forming a scan line and a gate on a substrate;

forming an oxide semiconductor layer and a first electrode layer on the substrate, the first electrode layer being in the same layer as the oxide semiconductor layer, the oxide semiconductor layer being disposed on the gate and comprising a channel region;

forming a source, a drain and a data line on the substrate, the first electrode layer being surrounded by the scan line and the data line, the source and the drain being respectively electrically connected to the oxide semiconductor layer, wherein the gate, the oxide semiconductor layer, the source and the drain form a thin-film transistor, and the thin-film transistor is electrically connected to the scan line and the data line;

forming a protective layer covering the source, the drain, the oxide semiconductor layer, the first electrode layer and the substrate; and

forming a second electrode layer on the first electrode layer, the protective layer being located between the first electrode layer and the second electrode layer, wherein one of the first and second electrode layers is electrically connected to the thin-film transistor, and the other is connected to a common voltage, and wherein the second electrode layer comprises a plurality of slits exposing an area of the first electrode layer.

9. The fabricating method of a pixel structure according to claim 8, wherein a method of forming the scan line and the gate comprises forming a first conductive material layer on the substrate, and patterning the first conductive material layer to form the scan line and the gate.

10. The fabricating method of a pixel structure according to claim 8, further comprising forming a gate insulating layer covering the gate and located between the gate and the oxide semiconductor layer.

11. The fabricating method of a pixel structure according to claim 8, wherein a method of forming the oxide semiconductor layer and the first electrode layer comprises:

forming an oxide semiconductor material layer on the substrate; and

patterning the oxide semiconductor material layer to form the oxide semiconductor layer and the first electrode layer, wherein the oxide semiconductor layer is located above the gate and the first electrode layer is surrounded by the scan line and the data line.

12. The fabricating method of a pixel structure according to claim 11, further comprising:

forming an insulating layer on the oxide semiconductor layer to cover the channel region of the oxide semiconductor layer.

13. The fabricating method of a pixel structure according to claim 12, wherein a method of forming the source, the drain and the data line comprises forming a second conductive material layer on the substrate to cover the insulating layer, and patterning the second conductive material layer to form the source, the drain and the data line.

14. The fabricating method of a pixel structure according to claim 8, further comprising performing a surface modification treatment on the first electrode layer, the surface modification treatment comprising an argon plasma process or a hydrogen plasma process.

15. The fabricating method of a pixel structure according to claim 8, wherein a method of forming the first electrode layer comprises making the first electrode in direct contact with the drain of the thin-film transistor.

16. The fabricating method of a pixel structure according to claim 8, further comprising forming a contact opening in the protective layer to expose the drain, and filling the second electrode layer into the contact opening so that the second electrode layer is in contact with the drain of the thin-film transistor.

17. The fabricating method of a pixel structure according to claim 8, wherein materials of the oxide semiconductor layer comprise indium gallium zinc oxide (IGZO), indium tin zinc oxide (ITZO), indium gallium oxide (IGO) or indium zinc oxide (IZO).